Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
139 words
A semiconductor memory device comprising memory cell arrays having a plurality of memory cells, a plurality of bit lines and a plurality of word lines connected respectively thereto, and I/O lines extending in the direction of said word lines and connected with a given number of bit lines of said plural bit lines via a selection circuit, said plural bit lines being divided into a first and a second bit line groups of a given number of lines, said I/O lines having a first I/O line connected to a given number of lines in said first bit line group via said selection circuit and a second I/O line connected to a given number of lines in said second bit line group via said selection circuit, and said first and second I/O lines being provided to extend in opposite directions.
Claim 2
Dependent Claim
34 words
The semiconductor memory device as claimed in Claim 1, wherein each of said first I/O line and said second I/O line has two signal line pairs each pair of which consists of two lines.
Claim 3
Dependent Claim
40 words
The semiconductor memory device as claimed in Claim 1, therein said first I/O line and said second I/O line are respectively connected to a first common data bus and a second common data bus via respective I/O line selection circuits.
Claim 4
Dependent Claim
43 words
The semiconductor memory device as claimed in Claim 3, wherein said first common data bus and said second common data bus are connected to respective input/output pads that are provided on the side of the two opposing longer sides of the semiconductor chip.
Claim 5
Dependent Claim
30 words
The semiconductor memory device as claimed in Claim 4, wherein said input/output pads respectively are disposed on the two opposing longer sides of the semiconductor chip in an equal number.
Claim 6
Dependent Claim
29 words
The semiconductor memory device as claimed in Claim 1, wherein said first bit line group and said second bit line group are the bit lines of an equal number.
Claim 7
Dependent Claim
49 words
The semiconductor memory device as claimed in Claim 4 or 5 wherein said first common data bus and said second common data bus comprise signal lines in a number equal to the number of the input/output pads that are disposed on either one of the two opposing longer sides.
Claim 8
Dependent Claim
53 words
The semiconductor memory device as claimed in Claim 4 or 5 wherein said first common data and said second common data bus come in a number which is equal to the number of the input/output pads disposed on either one of the two opposing longer sides and the number of signal line pairs.
Claim 9
Dependent Claim
65 words
The semiconductor memory device as claimed in claim 3, wherein said plural memory cell arrays are arranged with their sides in the word line direction adjoining to one another, and said first I/O line and said second I/O line connected to respective memory cell arrays are connected to said first common data bus and said second common data bus via respective I/O line selection circuits.
Claim 10
Dependent Claim
139 words
The semiconductor memory device as claimed in claim 3, wherein said plural memory cell arrays are arranged with their sides in the word line direction adjoining to one another, said first I/O lines connected to a given number of memory cell arrays are connected to said first common data bus via the I/O line selection circuit, said first I/O lines that are connected to the remaining memory cell arrays are connected to the second common data bus via the I/O line selection circuit, said second I/O lines connected to a given number of said memory cell arrays are connected to a third common data bus via the I/O line selection circuit, and the second I/O lines that are connected to the remaining memory cell arrays are connected to a fourth common data bus via the I/O line selection circuit.