Patent US5583450A successfully refreshed from Google Patents.
US5583450A
Expired / Lapsed
US
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Sequencer for a time multiplexed programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-08-18
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Granted: 1996-12-10
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Expires: 2015-08-18
Abstract
Abstract A programmable logic device (PLD) includes at least one configurable element, a plurality of programmable logic elements for configuring the configurable element(s), and a sequencer coupled to the plurality of programmable logic elements. Each programmable logic element typically includes a plurality of memory cells, wherein the sequencer accesses one of the plurality of memory cells during one step in a sequence of steps, each step initiated by one or more trigger signals. If the sequencer receives a plurality of trigger signals simultaneously, then the sequencer prioritizes these signals. Generally, each step provides one configuration of the PLD. In one embodiment, the sequence of steps includes less than all configurations of the PLD. In another embodiment, one trigger signal initiates a plurality of sequences of configurations.
Inventors
- 👤 Stephen M. Trimberger
- 👤 Richard A. Carberry
- 👤 Robert A. Johnson
- 👤 Jennifer Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17752; H03K19/17704
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
77 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells and means for selecting memory cell; and a sequencer coupled to said means for selecting, wherein said sequencer directs said means for selecting to access one of said plurality of memory cells during one step in a sequence of steps.
Claim 2
Dependent Claim
77 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells and means for selecting memory cell; and a sequencer coupled to said means for selecting, wherein said sequencer directs said means for selecting to access one of said plurality of memory cells during one step in a sequence of steps.
Claim 3
Dependent Claim
24 words
The programmable logic device of claim 1 further including a storage device for storing a plurality of intermediate states of one configurable logic element.
Claim 4
Dependent Claim
15 words
The programmable logic device of claim 1 wherein said configurable elements include an interconnect structure.
Claim 5
Dependent Claim
23 words
The programmable logic device of claim 1 further including at least one trigger signal, wherein one trigger signal initiates at least one configuration.
Claim 6
Dependent Claim
18 words
The programmable logic device of claim 1 wherein each step provides one configuration of said programmable logic device.
Claim 7
Dependent Claim
23 words
The programmable logic device of claim 1 wherein said sequencer receives input signals from at least one pin on said programmable logic device.
Claim 8
Dependent Claim
81 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element wherein at least one programmable logic element includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer receives signals from said interconnect structure.
Claim 9
Dependent Claim
81 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element wherein at least one programmable logic element includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer receives signals from said interconnect structure.
Claim 10
Dependent Claim
22 words
The programmable logic device of claim 7 wherein said signals include an address of a next configuration of said programmable logic device.
Claim 11
Dependent Claim
25 words
The programmable logic device of claim 7 wherein said signals include a jump command indicating to jump to an address on a subsequent clock cycle.
Claim 12
Dependent Claim
31 words
The programmable logic device of claim 9 wherein said sequencer is configurable to ignore said jump command, wherein if said jump command is ignored, then said sequencer uses a stored sequence.
Claim 13
Dependent Claim
16 words
The programmable logic device of claim 8 wherein said signals include a plurality of different addresses.
Claim 14
Dependent Claim
87 words
A programmable logic device comprising: at least one configurable element including an interconnect structure; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer outputs a current configuration address to said interconnect.
Claim 15
Dependent Claim
87 words
A programmable logic device comprising: at least one configurable element including an interconnect structure; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer outputs a current configuration address to said interconnect.
Claim 16
Dependent Claim
84 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic elements includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and wherein said sequencer includes a table of duration values for each configuration.
Claim 17
Dependent Claim
84 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic elements includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and wherein said sequencer includes a table of duration values for each configuration.
Claim 18
Dependent Claim
17 words
The programmable logic device of claim 13 wherein one duration value controls the duration of one configuration.
Claim 19
Dependent Claim
17 words
The programmable logic device of claim 13 wherein at least one of said duration values is fixed.
Claim 20
Dependent Claim
25 words
The programmable logic device of claim 13 wherein at least one of said duration values is variable for each design of said programmable logic device.
Claim 21
Dependent Claim
21 words
The programmable logic device of claim 13 wherein one of duration value varies from one micro cycle to another micro cycle.
Claim 22
Dependent Claim
88 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and a prioritizer to prioritize signals if two or more trigger signals are received simultaneously by said sequencer.
Claim 23
Dependent Claim
88 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and a prioritizer to prioritize signals if two or more trigger signals are received simultaneously by said sequencer.
Claim 24
Dependent Claim
23 words
The programmable logic device of claim 18 further including means to store pending trigger signals if said sequencer is in an active mode.
Claim 25
Dependent Claim
103 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a first sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and a second sequencer, wherein said first sequencer controls sequencing for a first set of said configurable elements and said second sequencer controls sequencing for a second set of said configurable elements.
Claim 26
Dependent Claim
103 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a first sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and a second sequencer, wherein said first sequencer controls sequencing for a first set of said configurable elements and said second sequencer controls sequencing for a second set of said configurable elements.
Claim 27
Dependent Claim
83 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at lease one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer receives input signals from one or more configurable elements.
Claim 28
Dependent Claim
83 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at lease one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer receives input signals from one or more configurable elements.
Claim 29
Dependent Claim
16 words
The programmable logic device of claim 21 wherein said input signals include a jump command signal.
Claim 30
Dependent Claim
16 words
The programmable logic device of claim 21 wherein said input signals include a jump address signal.
Claim 31
Dependent Claim
17 words
The programmable logic device of claim 21 wherein said input signals include at least one trigger signal.
Claim 32
Dependent Claim
97 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring sold at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, wherein each step provides one configuration of said programmable logic device, and wherein said sequence of steps includes less than all configurations of said programmable logic device.
Claim 33
Dependent Claim
97 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring sold at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, wherein each step provides one configuration of said programmable logic device, and wherein said sequence of steps includes less than all configurations of said programmable logic device.
Claim 34
Dependent Claim
83 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer receives input signals from said programmable logic elements.
Claim 35
Dependent Claim
83 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable element, wherein at least one programmable logic element includes a plurality of memory cells; and a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps, and wherein said sequencer receives input signals from said programmable logic elements.
Claim 36
Dependent Claim
84 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable elements, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and means for storing an address of a configuration and returning to said address.
Claim 37
Dependent Claim
84 words
A programmable logic device comprising: at least one configurable element; a plurality of programmable logic elements for configuring said at least one configurable elements, wherein at least one programmable logic element includes a plurality of memory cells; a sequencer coupled to at least one of said plurality of programmable logic elements, wherein said sequencer accesses one of said plurality of memory cells during one step in a sequence of steps; and means for storing an address of a configuration and returning to said address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |