US5583445A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Opto-electronic membrane probe
Assignee: The AT&T MVPD Group LLC
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Filing: 1994-02-04
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Granted: 1996-12-10
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Expires: 2014-02-04
Abstract
Abstract A probe for testing very high frequency circuit chips (34) includes a flexible membrane (12) having test probe contacts (14), arranged to contact pads (32) on the device under test to bias up, drive and load down the circuit under test. Various optically-addressable devices (68,130,202) are mounted on the membrane and either excited or probed by a laser beam (66) to transmit and/or sense very high frequency electrical signals to/from the device under test. The optically-addressable devices are excited or probed by a high bandwidth laser (64,66), and thus very high speed circuits may be driven by contact pads on the probe membrane and probed by a laser beam. Employing an optically transparent membrane (200) having test probe contacts (206,208) for bias, driving and loading a circuit under test, and having an electro-optic polymer layer (102, 202), a probing laser beam (204) may be directed through the membrane and the electro-optic polymer layer to sample an RF field generated by a device (214) under test. Measurement of internal circuit node voltage wave forms in the electro-optic substrate of a device (34, 50) under test may be accomplished by using test probe contacts (14, 55) to bias, drive and load the device under test while transmitting a laser probe beam (46, 76) through the membrane and electro-optic substrate.
Inventors
- 👤 Ruth A. Mullen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:29
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/0735; G01R31/00; G01R31/28; G01R31/302; G01R31/308; G01R31/311
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
189 words
A test probe for testing high speed circuits of an integrated circuit chip comprising: a flexible membrane having an outer surface, a plurality of test probe contacts on said surface configured and arranged to contact pads of a device to be tested, said test probe contacts including a first group of contacts configured and arranged to provide power, bias and loading to circuits of said chip, a plurality of conductive traces on said membrane connected to respective ones of said test probe contacts and configured and arranged for connection to test circuitry, and an optically-addressable device mounted to said membrane, wherein the optically-addressable device is comprised of an electro-optic polymer layer laminated to the flexible membrane, said contacts and traces being formed on said electro-optic layer, and wherein some of the conductive traces on said membrane are transmission lines laminated onto the electro-optic polymer layer of the membrane and have ends adapted to be contacted to pads of the device under test, said transmission lines being configured and arranged to sustain an electrical standing wave when two ends of said transmission lines are contacted to pads of a device-under-test.
Claim 2
Dependent Claim
189 words
A test probe for testing high speed circuits of an integrated circuit chip comprising: a flexible membrane having an outer surface, a plurality of test probe contacts on said surface configured and arranged to contact pads of a device to be tested, said test probe contacts including a first group of contacts configured and arranged to provide power, bias and loading to circuits of said chip, a plurality of conductive traces on said membrane connected to respective ones of said test probe contacts and configured and arranged for connection to test circuitry, and an optically-addressable device mounted to said membrane, wherein the optically-addressable device is comprised of an electro-optic polymer layer laminated to the flexible membrane, said contacts and traces being formed on said electro-optic layer, and wherein some of the conductive traces on said membrane are transmission lines laminated onto the electro-optic polymer layer of the membrane and have ends adapted to be contacted to pads of the device under test, said transmission lines being configured and arranged to sustain an electrical standing wave when two ends of said transmission lines are contacted to pads of a device-under-test.
Claim 3
Dependent Claim
25 words
The test probe of claim 1 wherein said optically-addressable device comprises means on said membrane responsive to an optical signal for generating an electrical signal.
Claim 4
Dependent Claim
27 words
The test probe of claim 1 wherein said optically-addressable device comprises electro-optic material that modulates an optical signal in the presence of a radio frequency signal therein.
Claim 5
Dependent Claim
47 words
The test probe of claim 1 for testing a device under test having an electro-optic substrate, wherein the optically-addressable device includes a transparent window in the flexible membrane having a predetermined position relative to the substrate of the device-under-test for passing an optical signal to said substrate.
Claim 6
Dependent Claim
48 words
The test probe of claim 1 for testing a device under test having a semi-conductor substrate, and wherein the optically-addressable device includes a transparent window in the flexible membrane having a predetermined position relative to the substrate of the device-under-test for passing an optical signal to said substrate.
Claim 7
Dependent Claim
43 words
The test probe of claim 1 wherein the electro-optic polymer layer is laminated onto the outer surface of the flexible membrane such that the electro-optic polymer layer can be held in very close proximity to selected co-planar features of interest on the device-under-test.
Claim 8
Dependent Claim
20 words
The test probe of claim 1 wherein said optically-addressable device is a high frequency photoconductive switch mounted on said membrane.
Claim 9
Dependent Claim
20 words
The test probe of claim 7 wherein said high frequency photoconductive switch is configured to be an electrical pulse generator.
Claim 10
Dependent Claim
19 words
The test probe of claim 7 wherein said high frequency photoconductive switch is configured to be a sampling gate.
Claim 11
Dependent Claim
20 words
The test probe of claim 7 wherein said high frequency photoconductive switch is configured to be a frozen wave generator.
Claim 12
Dependent Claim
19 words
The test probe of claim 7 wherein said high frequency photoconductive switch is configured to be an RF mixer.
Claim 13
Dependent Claim
20 words
The test probe of claim 7 wherein said high frequency photoconductive switch is configured to be an RF burst generator.
Claim 14
Dependent Claim
24 words
The test probe of claim 7 wherein said high frequency photoconductive switch is integrated to signal processing circuitry to form an opto-electronic integrated circuit.
Claim 15
Dependent Claim
26 words
The test probe of claim 13 wherein said opto-electronic integrated circuit is a high-bandwidth photoconductor integrated to a high bandwidth amplifier to form an optical receiver.
Claim 16
Dependent Claim
31 words
The test probe of claim 1 including means for directing a laser beam at said optically-addressable device, and means for directing a polarized laser beam through said membrane to said device-under-test.
Claim 17
Dependent Claim
39 words
The test probe of claim 1 wherein said optically-addressable device comprises a plurality of high frequency photoconductive switches mounted on said membrane configured in a six-gap arrangement for making measurements of the S-parameters of a component of the device-under-test.
Claim 18
Dependent Claim
158 words
A test probe for testing high speed circuits of an integrated circuit chip having an electro-optic substrate and including an RF signal line that produces electromagnetic radio frequency field lines in the substrate, the substrate having a reflective ground plane on a lower surface, said test probe comprising: a flexible transparent membrane having an outer surface, a plurality of test probe contacts on said surface configured and arranged to contact pads of a circuit to be tested and to provide power, bias and loading for said circuit, a plurality of conductive traces on said membrane connected to respective ones of said test probe contacts and configured and arranged for connection to test circuitry, means for transmitting a polarized laser beam through said transparent membrane and through said field lines in the substrate for reflection from said ground plane, the laser beam being modulated during transmission through the substrate, and means for sensing the modulation to test said circuit.
Claim 19
Dependent Claim
158 words
A test probe for testing high speed circuits of an integrated circuit chip having an electro-optic substrate and including an RF signal line that produces electromagnetic radio frequency field lines in the substrate, the substrate having a reflective ground plane on a lower surface, said test probe comprising: a flexible transparent membrane having an outer surface, a plurality of test probe contacts on said surface configured and arranged to contact pads of a circuit to be tested and to provide power, bias and loading for said circuit, a plurality of conductive traces on said membrane connected to respective ones of said test probe contacts and configured and arranged for connection to test circuitry, means for transmitting a polarized laser beam through said transparent membrane and through said field lines in the substrate for reflection from said ground plane, the laser beam being modulated during transmission through the substrate, and means for sensing the modulation to test said circuit.
Claim 20
Dependent Claim
45 words
The test probe of claim 17 including an optically addressable switch on said membrane, and a laser for activating said switch, said switch being connected to some of said test probe contacts for driving said circuits at very high frequency in response to said laser.
Claim 21
Dependent Claim
166 words
A test probe for testing a high speed circuit of an integrated circuit chip comprising: a flexible membrane having an outer surface, an electro-optic layer laminated to said outer surface, a plurality of test probe contacts on said electro-optic layer outer surface configured and arranged to contact pads of a device to be tested and to provide power, bias and loading for said high speed circuit, a plurality of conductive traces on said electro-optic layer outer surface connected to respective ones of said test probe contacts and configured and arranged for connection to test circuitry, a high frequency transmission line on said electro-optic layer outer surface having a pair of said test probe contacts at one end for contacting pads of said integrated circuit chip, said transmission line on said electro-optic layer outer surface having circuit node voltage wave forms generated by test signals applied via said test probe contacts, and means for directing a laser probe beam at said electro-optic layer adjacent the transmission line.
Claim 22
Dependent Claim
166 words
A test probe for testing a high speed circuit of an integrated circuit chip comprising: a flexible membrane having an outer surface, an electro-optic layer laminated to said outer surface, a plurality of test probe contacts on said electro-optic layer outer surface configured and arranged to contact pads of a device to be tested and to provide power, bias and loading for said high speed circuit, a plurality of conductive traces on said electro-optic layer outer surface connected to respective ones of said test probe contacts and configured and arranged for connection to test circuitry, a high frequency transmission line on said electro-optic layer outer surface having a pair of said test probe contacts at one end for contacting pads of said integrated circuit chip, said transmission line on said electro-optic layer outer surface having circuit node voltage wave forms generated by test signals applied via said test probe contacts, and means for directing a laser probe beam at said electro-optic layer adjacent the transmission line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |