Patent US5583364A successfully refreshed from Google Patents.
US5583364A
Expired / Lapsed
US
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Semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1995-08-04
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Granted: 1996-12-10
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Expires: 2015-08-04
Abstract
Abstract A semiconductor device improved not to form a parasitic gate overlap capacitance in a drain side of an MOS transistor. A first gate electrode and a second gate electrode are provided on a semiconductor substrate. A common drain electrode is provided between first gate electrode and second gate electrode in a main surface of silicon substrate. Common drain region includes a high concentration impurity region and a pair of low concentration impurity regions. Outer edges of low concentration impurity regions are located coplanar with a side surface of gate electrodes.
Inventors
- 👤 Mitsuyoshi Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/603; H10D30/605; H10D30/611; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
480 words
A semiconductor device, comprising: a semiconductor substrate; a first gate electrode and a separate second gate electrode provided on said semiconductor substrate so as to be parallel to each other; a first gate oxide film provided between said semiconductor substrate and said first gate electrode; a second gate oxide film provided between said semiconductor substrate and said second gate electrode; a common drain region provided between said first gate electrode and said second gate electrode in a surface of said semiconductor substrate; a first source region provided opposite to said common drain region with said first gate electrode therebetween in the surface of said semiconductor substrate; and a second source region provided opposite to said common drain region with said second gate electrode therebetween in the surface of said semiconductor substrate; wherein said common drain region includes a high concentration impurity region extending in a direction of said first and second gate electrodes and a low concentration impurity region provided on each side of the high concentration impurity region, an outer edge of one of said low concentration impurity regions being located coplanar with a side surface of said first gate electrode proximate said common drain region, and an outer edge of the other of said low concentration impurity regions being located coplanar with a side surface of said second gate electrode proximate said common drain region, wherein said first source region includes (a) a first high concentration impurity region provided furthermost from said first gate electrode and extending in a direction of said first gate electrode, (b) a first medium concentration impurity region having lower concentration than said first high concentration impurity region, provided adjacent to said first high concentration impurity region and extending in a direction of said first gate electrode, and (c) a first low concentration impurity region having lower concentration than said first medium concentration impurity region, provided adjacent to said first medium concentration impurity region and nearest to said first gate electrode and extending in a direction of said first gate electrode, an outer edge of said first low concentration impurity region extending under said first gate electrode; and wherein said second source region includes (d) a second high concentration impurity region provided furthermost from said second gate electrode and extending in a direction of said second gate electrode, (e) a second medium concentration impurity region having lower concentration than said second high concentration impurity region, provided adjacent to said second high concentration impurity region and extending in a direction of said second gate electrode, and (f) a second low concentration impurity region having lower concentration than said second medium concentration impurity region, provided adjacent to said second medium concentration impurity region and nearest to said second gate electrode and extending in a direction of said second gate electrode, an outer edge of said second low concentration impurity region extending under said second gate electrode.
Claim 2
Dependent Claim
480 words
A semiconductor device, comprising: a semiconductor substrate; a first gate electrode and a separate second gate electrode provided on said semiconductor substrate so as to be parallel to each other; a first gate oxide film provided between said semiconductor substrate and said first gate electrode; a second gate oxide film provided between said semiconductor substrate and said second gate electrode; a common drain region provided between said first gate electrode and said second gate electrode in a surface of said semiconductor substrate; a first source region provided opposite to said common drain region with said first gate electrode therebetween in the surface of said semiconductor substrate; and a second source region provided opposite to said common drain region with said second gate electrode therebetween in the surface of said semiconductor substrate; wherein said common drain region includes a high concentration impurity region extending in a direction of said first and second gate electrodes and a low concentration impurity region provided on each side of the high concentration impurity region, an outer edge of one of said low concentration impurity regions being located coplanar with a side surface of said first gate electrode proximate said common drain region, and an outer edge of the other of said low concentration impurity regions being located coplanar with a side surface of said second gate electrode proximate said common drain region, wherein said first source region includes (a) a first high concentration impurity region provided furthermost from said first gate electrode and extending in a direction of said first gate electrode, (b) a first medium concentration impurity region having lower concentration than said first high concentration impurity region, provided adjacent to said first high concentration impurity region and extending in a direction of said first gate electrode, and (c) a first low concentration impurity region having lower concentration than said first medium concentration impurity region, provided adjacent to said first medium concentration impurity region and nearest to said first gate electrode and extending in a direction of said first gate electrode, an outer edge of said first low concentration impurity region extending under said first gate electrode; and wherein said second source region includes (d) a second high concentration impurity region provided furthermost from said second gate electrode and extending in a direction of said second gate electrode, (e) a second medium concentration impurity region having lower concentration than said second high concentration impurity region, provided adjacent to said second high concentration impurity region and extending in a direction of said second gate electrode, and (f) a second low concentration impurity region having lower concentration than said second medium concentration impurity region, provided adjacent to said second medium concentration impurity region and nearest to said second gate electrode and extending in a direction of said second gate electrode, an outer edge of said second low concentration impurity region extending under said second gate electrode.
References Cited (Backward Citations)
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