Method and apparatus for managing live insertion of CPU and I/O boards into a computer system

Claim 2

A bus control module comprising: a data interface having a first flag, when set, denoting the bus control module as a potential system test master responsible for conducting system level testing to any CPU or I/O board arbitrating to be a system test master, the CPU or I/O board(s) being interconnected to a system bus through bus connector slot(s) of the system bus, wherein power application to the bus connector slot(s) and performance of bus operations on the system bus are both controlled by the bus control module; and a micro-controller coupled to the data interface for ensuring the first flag is in the set state if and when a live inserted CPU or I/O board arbitrates to be the system test master, thereby always injecting the bus control module in the system test master arbitration.

Claim 3

The bus control module as set forth in claim 1, wherein the bus connector slots are ordered, with the bus control module by convention occupying the lowest order bus connector bus slot; the live inserted CPU or I/O board, upon being provided with power, performs a self test, and when completed, sets a second flag, accessible from the system bus, denoting the self test was completed; the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrates to be system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; the micro-controller sets the first flag whenever a live insertion is detected, and clears the first flag after sufficient time has elapsed for system test master arbitration; and the micro-controller upon winning system test master arbitration by default neither clears the second flag of the live inserted CPU or I/O board, nor initiates/masters any system test.

Claim 4

The bus control module as set forth in claim 1, wherein the bus connector slots are ordered, with the bus control module by convention occupying the lowest order bus connector slot; the live inserted CPU or I/O board, upon being provided with power, performs a self test, and when completed, sets a second flag, accessible from the system bus, denoting the self test was completed; the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrates to be system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; the micro-controller sets the first flag after power on/reset initialization, and leaves the first flag in the set state for the entire time during operation; and the micro-controller upon winning system test master arbitration by default neither clears the second flag of the live inserted CPU or I/O board, nor initiates/masters any system test.

Claim 5

The bus control module as set forth in claim 1, wherein the bus connector slots are ordered, with the bus control module by convention occupying the lowest order bus connector slot; the live inserted CPU or I/O board, upon being provided with power, performs a self test, and when completed, sets a second flag, accessible from the system bus, denoting the self test was completed; the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrates to be system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; the micro-controller sets the first flag during power on/reset initialization to arbitrate to be system test master, and leaves the first flag in the set state for the entire time during operation; and the micro-controller upon winning system test master arbitration by default neither clears the second flag of the live inserted CPU or I/O board, nor initiates/masters any system test.

Claim 6

A computer system comprising: a processor board having at least one processor for executing instructions; a memory board having at least one memory module for storing data; and a system board having a system bus assembly against which the processor and memory boards are coupled, the system bus assembly further including a plurality of bus connector slots for removably coupling a corresponding plurality of CPU or I/O boards, and a bus control module having: a data interface including a first flag, when set, denoting the bus control module as a potential system test master responsible for conducting system level testing to any CPU or I/O board arbitrating to be system test master, the CPU or I/O board(s) being interconnected to the system bus through the bus connector slot(s), wherein power application to the bus connector slots and performance of bus operations on the system bus are both controlled by the bus control module, and a micro-controller coupled to the data interface for ensuring the first flag is in the set state if and when a live inserted CPU or I/O board arbitrates to be system test master, thereby injecting the bus control module in the system test master arbitration.

Claim 7

A computer system comprising: a processor board having at least one processor for executing instructions; a memory board having at least one memory module for storing data; and a system board having a system bus assembly against which the processor and memory boards are coupled, the system bus assembly further including a plurality of bus connector slots for removably coupling a corresponding plurality of CPU or I/O boards, and a bus control module having: a data interface including a first flag, when set, denoting the bus control module as a potential system test master responsible for conducting system level testing to any CPU or I/O board arbitrating to be system test master, the CPU or I/O board(s) being interconnected to the system bus through the bus connector slot(s), wherein power application to the bus connector slots and performance of bus operations on the system bus are both controlled by the bus control module, and a micro-controller coupled to the data interface for ensuring the first flag is in the set state if and when a live inserted CPU or I/O board arbitrates to be system test master, thereby injecting the bus control module in the system test master arbitration.

Claim 8

The computer system as set forth in claim 5, wherein the bus connector slots are ordered with the bus control module by convention occupying the lowest order bus connector slot; the live inserted CPU or I/O board, upon being provided with power, performs a self test, and if completed successfully, sets a second flag, accessible from the system bus, denoting the self test was completed successfully; the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrates to be system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; the micro-controller sets the first flag whenever a live insertion is detected, and clears the first flag after sufficient time has elapsed to for system test master arbitration; and the micro-controller upon winning system test master arbitration by default neither clears the second flag of the live inserted CPU or I/O board, nor initiates/masters any system test.

Claim 9

The computer system as set forth in claim 5, wherein the bus connector slots are ordered, with the bus control module by convention occupying the lowest order bus connector slot; the live inserted CPU or I/O board, upon being provided with power, performs a self test, and when completed, sets a second flag, accessible from the system bus, denoting the self test was completed; the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrates to be system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; the micro-controller sets the first flag after power on/reset initialization, and leaves the first flag in the set state for the entire time during operation; and the micro-controller upon winning system test master arbitration by default neither clears the second flag of the live inserted CPU or I/O board, nor initiates/masters any system test.

Claim 10

The computer system as set forth in claim 5, wherein the bus connector slots are ordered, with the bus control module by convention occupying the lowest order Bus connector slot; the live inserted CPU or I/O board, upon being provided with power, performs a self test, and when completed, sets a second flag, accessible from the system bus, denoting the self test was completed; the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrates to be system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; the micro-controller sets the first flag during power on/reset initialization to arbitrate to be system test master, and leaves the first flag in the set state for the entire time during operation; and the micro-controller upon winning system test master arbitration by default neither clears the second flag of the live inserted CPU or I/O board, nor initiates/masters any system test.

Claim 11

In a computer system comprising a system bus assembly including a system bus, a plurality of bus connector slots for removably coupling a corresponding plurality of CPU or I/O boards to the system bus, and a bus control module for controlling power application to the bus connector slots as well as performance of bus operations on the system bus, a method for managing live insertion of a CPU or I/O board into one of the bus connector slot, the method comprising the steps of: a) the bus control module injecting itself into and winning each system test master arbitration resulted from a live insertion of a CPU or I/O board; b) the bus control module leaving the live inserted CPU or I/O board to think its participation in system wide testing is undesired by the system test master; and c) the bus control module refraining from initiating and mastering any system test notwithstanding its winning of system test master arbitration.

Claim 12

In a computer system comprising a system bus assembly including a system bus, a plurality of bus connector slots for removably coupling a corresponding plurality of CPU or I/O boards to the system bus, and a bus control module for controlling power application to the bus connector slots as well as performance of bus operations on the system bus, a method for managing live insertion of a CPU or I/O board into one of the bus connector slot, the method comprising the steps of: a) the bus control module injecting itself into and winning each system test master arbitration resulted from a live insertion of a CPU or I/O board; b) the bus control module leaving the live inserted CPU or I/O board to think its participation in system wide testing is undesired by the system test master; and c) the bus control module refraining from initiating and mastering any system test notwithstanding its winning of system test master arbitration.

Claim 13

The method as set forth in claim 9, wherein, the bus connector slots being ordered, with the bus control module by convention occupying the lowest order bus connector bus slot; said method further comprises the steps of: d) the live inserted CPU or I/O board, upon being provided with power, performing a self test, and when completed, setting a second flag, accessible from the system bus, denoting the self test was completed, and e) the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrating to be the system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, and the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; said step (a) comprises the steps of: a.1) the bus control module monitoring for live insertion of a CPU or I/O board into one of the bus connector slots, a.2) the bus control module, responsive to a detection, setting a first flag to denote to the live inserted CPU or I/O board that the bus control module is a potential system test master before allowing power to be applied to the bus connector slot against which the CPU or I/O board is live inserted, and a.3) the bus control module resetting the first flag when system test master arbitration is completed.

Claim 14

The method as set forth in claim 9, wherein, the bus connector slots being ordered, with the bus control module by convention occupying the lowest order bus connector bus slot; said method further comprises the steps of: d) the live inserted CPU or I/O board, upon being provided with power, performing a self test, and when completed, setting a second flag, accessible from the system bus, denoting the self test was completed, and e) the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrating to be the system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, and the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; said step (a) comprises the bus control module setting the first flag after power on/reset initialization, and leaving the first flag in the set state for the entire time during operation.

Claim 15

The method as set forth in claim 9, wherein, the bus connector slots being ordered, with the bus control module by convention occupying the lowest order bus connector bus slot; said method further comprises the steps of: d) the live inserted CPU or I/O board, upon being provided with power, performing a self test, and when completed, setting a second flag, accessible from the system bus, denoting the self test was completed, and e) the live inserted CPU or I/O board, if eligible to be a system test master, further arbitrating to be the system test master by iteratively checking for any potential system test master occupying a lower ordered bus connector slot, and the live inserted CPU or I/O board giving up system test master arbitration whenever detecting a potential system test master at a lower ordered bus connector slot; said step (a) comprises the bus control module setting the first flag during power on/reset initialization to arbitrate to be system test master, and leaving the first flag in the set state for the entire time during operation.