Semiconductor integrated circuit device with input-protecting circuit

Claim 2

A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first conductivity type; a buried layer having a second conductivity type opposite to said first conductivity type formed on a surface of said semiconductor substrate; a semiconductor layer having said second conductivity type formed on said buried layer; a first well of said first conductivity type formed in said semiconductor layer; a second well of said first conductivity type formed in said semiconductor layer and electrically isolated from said first well; a second conductivity type-MOS transistor formed in said first well and having first and second impurity regions having said second conductivity type and a gate, said first impurity region grounded, the second impurity region connected to an input terminal to which an external signal is input, and the gate grounded and connected to said first impurity region; and an impurity region having said second conductivity type grounded and formed in said second well, wherein when a surge voltage is applied to the input terminal, a current path is formed by way of said input terminal, the second impurity region of said second conductivity type-MOS transistor formed in said first well, said buried layer, the grounded impurity region formed in said second well, and a ground terminal.

Claim 3

A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first conductivity type; a buried layer having a second conductivity type opposite to said first conductivity type formed on a surface of said semiconductor substrate; an epitaxial layer having said second conductivity type formed on said buried layer; first and second wells each of said first conductivity type formed in said epitaxial layer spaced apart from each other and electrically isolated from each other; an impurity region having said first conductivity type formed in said first well, to which a substrate bias voltage is applied; a second conductivity type-MOS transistor formed in said first well and having first and second impurity regions having said second conductivity type and a gate, the gate connected to an input terminal and said first impurity region grounded; an impurity region having said first conductivity type formed in said second well, to which a substrate bias voltage is applied; and an input-protecting second conductivity type-MOS transistor formed in said second well and having first and second impurity regions having said second conductivity type and a gate, the gate and said first impurity region both grounded and the second impurity region connected to the input terminal, wherein when a surge voltage is applied to the input terminal, circuits formed in the semiconductor substrate are protected by passing a first current by way of the input terminal, the second impurity region of said input-protecting second conductivity type-MOS transistor, said buried layer, said second conductivity type-MOS transistor formed in said first well, and a ground terminal, in addition to a second current flowing between the second impurity region and the first impurity region of said input-protecting second conductivity type-MOS transistor.

Claim 4

A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first conductivity type; a buried layer having a second conductivity type opposite to said first conductivity type formed on a surface of said semiconductor substrate; an epitaxial layer having said second conductivity type formed on said buried layer; first and second wells each of said first conductivity type formed in said epitaxial layer spaced apart from each other and electrically isolated from each other; an impurity region having said first conductivity type formed in said first well, to which a substrate bias voltage is applied; a second conductivity type-MOS transistor formed in said first well and having first and second impurity regions having said second conductivity type and a gate, the gate connected to an input terminal and said first impurity region grounded; an impurity region having said first conductivity type formed in said second well, to which a substrate bias voltage is applied; and an input-protecting second conductivity type-MOS transistor formed in said second well and having first and second impurity regions having said second conductivity type and a gate, the gate and said first impurity region both grounded and the second impurity region connected to the input terminal, wherein when a surge voltage is applied to the input terminal, circuits formed in the semiconductor substrate are protected by passing a first current by way of the input terminal, the second impurity region of said input-protecting second conductivity type-MOS transistor, said buried layer, said second conductivity type-MOS transistor formed in said first well, and a ground terminal, in addition to a second current flowing between the second impurity region and the first impurity region of said input-protecting second conductivity type-MOS transistor.

Claim 5

A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first conductivity type; a buried layer having a second conductivity type opposite to said first conductivity type formed on a surface of said semiconductor substrate using an impurity diffusion method; an epitaxial layer having said second conductivity type formed on said buried layer using a vapor phase epitaxy method; first and second wells each of said first conductivity type formed in said epitaxial layer spaced apart from each other and electrically isolated from each other; a third well of said second conductivity type formed in said epitaxial layer and adjacent to said first well; an impurity region having said first conductivity type formed in said first well, to which a substrate bias voltage is applied; a second conductivity type-MOS transistor formed in said first well and having first and second impurity regions having said second conductivity type and a gate, the gate connected to an input terminal and said first impurity region grounded; an impurity region having said first conductivity type formed in said second well, to which a substrate bias voltage is applied; an input-protecting second conductivity type-MOS transistor formed in said second well and having first and second impurity regions having said second conductivity type and a gate, the gate and said first impurity region both grounded and the second impurity region connected to the input terminal; and a first conductivity type-MOS transistor formed in said third well and having first and second impurity regions having said first conductivity type and a gate, the second impurity region of said first conductivity type-MOS transistor connected to the second impurity region of said second conductivity type-MOS transistor, the gate of said first conductivity type-MOS transistor connected to the input terminal and the first impurity region of said first conductivity type-MOS transistor connected to a supply voltage terminal, wherein when a surge voltage is applied to the input terminal, circuits formed in the semiconductor substrate are protected by passing a first current by way of the input terminal, the second impurity region of said input-protecting second conductivity type-MOS transistor, said buried layer, the grounded first impurity region of said second conductivity type-MOS transistor and a ground terminal, in addition to a second current flowing between the second impurity region and the first impurity region of said input-protecting second conductivity type-MOS transistor.

Claim 6

A semiconductor integrated circuit device, comprising: a semiconductor substrate having a first conductivity type; a buried layer having a second conductivity type opposite to said first conductivity type formed on a surface of said semiconductor substrate using an impurity diffusion method; an epitaxial layer having said second conductivity type formed on said buried layer using a vapor phase epitaxy method; first and second wells each of said first conductivity type formed in said epitaxial layer spaced apart from each other and electrically isolated from each other; a third well of said second conductivity type formed in said epitaxial layer and adjacent to said first well; an impurity region having said first conductivity type formed in said first well, to which a substrate bias voltage is applied; a second conductivity type-MOS transistor formed in said first well and having first and second impurity regions having said second conductivity type and a gate, the gate connected to an input terminal and said first impurity region grounded; an impurity region having said first conductivity type formed in said second well, to which a substrate bias voltage is applied; an input-protecting second conductivity type-MOS transistor formed in said second well and having first and second impurity regions having said second conductivity type and a gate, the gate and said first impurity region both grounded and the second impurity region connected to the input terminal; and a first conductivity type-MOS transistor formed in said third well and having first and second impurity regions having said first conductivity type and a gate, the second impurity region of said first conductivity type-MOS transistor connected to the second impurity region of said second conductivity type-MOS transistor, the gate of said first conductivity type-MOS transistor connected to the input terminal and the first impurity region of said first conductivity type-MOS transistor connected to a supply voltage terminal, wherein when a surge voltage is applied to the input terminal, circuits formed in the semiconductor substrate are protected by passing a first current by way of the input terminal, the second impurity region of said input-protecting second conductivity type-MOS transistor, said buried layer, the grounded first impurity region of said second conductivity type-MOS transistor and a ground terminal, in addition to a second current flowing between the second impurity region and the first impurity region of said input-protecting second conductivity type-MOS transistor.

Claim 7

The semiconductor integrated circuit device of claim 1, wherein when said surge voltage is applied to the input terminal, said current path is formed by way of the input terminal, the second impurity region of said second conductivity type-MOS transistor formed in said first well acting as an emitter for a first parasitic bipolar transistor, said buried layer acting as a collector for said first parasitic bipolar transistor and as an emitter for a second parasitic bipolar transistor, said grounded impurity region formed in said second well acting as a collector for said second parasitic bipolar transistor, and said ground terminal.

Claim 8

The semiconductor integrated circuit device of claim 4, wherein said first well acts as a base for said first parasitic bipolar transistor and said second well acts as a base for said second parasitic bipolar transistor.

Claim 9

The semiconductor integrated circuit device of claim 5, wherein an impurity region having said first conductivity type to which a substrate bias voltage is applied is formed in said first well and acts as a base terminal for said first parasitic bipolar transistor and wherein an impurity region having said first conductivity type to which a substrate bias voltage is applied is formed in said second well and acts as a base terminal for said second parasitic bipolar transistor.

Claim 10

The semiconductor integrated circuit device of claim 2, wherein when said surge voltage is applied to the input terminal, said first current is passed by way of the input terminal, the second impurity region of said input-protecting second conductivity type-MOS transistor formed in said second well acting as an emitter for a first parasitic bipolar transistor, said buried layer acting as a collector for said first parasitic bipolar transistor and as an emitter for a second parasitic bipolar transistor, said grounded first impurity region of said second conductivity type-MOS transistor formed in said first well acting as a collector for said second parasitic bipolar transistor, and said ground terminal.

Claim 11

The semiconductor integrated circuit device of claim 7, wherein said first well acts as a base for said second parasitic bipolar transistor and said second well acts as a base for said first parasitic bipolar transistor.

Claim 12

The semiconductor integrated circuit device of claim 8, wherein said impurity region having said first conductivity type to which a substrate bias voltage is applied formed in said first well acts as a base terminal for said second parasitic bipolar transistor and wherein said impurity region having said first conductivity type to which a substrate bias voltage is applied formed in said second well acts as a base terminal for said first parasitic bipolar transistor.

Claim 13

The semiconductor integrated circuit device of claim 3, wherein when said surge voltage is applied to the input terminal, said first current is passed by way of the input terminal, the second impurity region of said input-protecting second conductivity type-MOS transistor formed in said second well acting as an emitter for a first parasitic bipolar transistor, said buried layer acting as a collector for said first parasitic bipolar transistor and as an emitter for a second parasitic bipolar transistor, said grounded first impurity region of said second conductivity type-MOS transistor formed in said first well acting as a collector for said second parasitic bipolar transistor, and said ground terminal.

Claim 14

The semiconductor integrated circuit device of claim 10, wherein said first well acts as a base for said second parasitic bipolar transistor and said second well acts as a base for said first parasitic bipolar transistor.

Claim 15

The semiconductor integrated circuit device of claim 11, wherein said impurity region having said first conductivity type to which a substrate bias voltage is applied formed in said first well acts as a base terminal for said second parasitic bipolar transistor and wherein said impurity region having said first conductivity type to which a substrate bias voltage is applied formed in said second well acts as a base terminal for said first parasitic bipolar transistor.