US5577220A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for saving and restoring the state of a CPU executing code in protected mode including estimating the value of the page table base register
Assignee: Lenovo Singapore Pte Ltd
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Filing: 1995-10-03
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Granted: 1996-11-19
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Expires: 2015-10-03
Abstract
Abstract A method of saving and restoring the state of a CPU operating code in protected mode on a computer system. The save method makes use of BIOS operating in shadow RAM located in a region where linear addresses equal physical addresses while saving the state of the CPU. The registers that cannot be directly saved to memory are determined by searching the system memory for data structures that correspond to the particular register. The restore method uses dummy page tables that point to the shadowed BIOS to allow the CPU to reenter protected mode without generating a protection fault.
Inventors
- 👤 James L. Combs
- 👤 Dwayne T. Crump
- 👤 Steven T. Pancoast
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1441; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4418
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
In a computer system having: (a) a processing unit; (b) a memory circuit having addressable memory locations in circuit communication with the processing unit; and (c) a memory manager in circuit communication with the processing unit and the memory circuit, the memory manager having a page directory base register associated therewith for affecting accesses by the processing unit to the memory circuit and associating a linear address to a physical address of the memory locations in the memory circuit; a method of estimating the value of the page directory base register, comprising the steps of: (1) locating a page translation table by searching at least a subset of all physical memory for a page translation table; (2) determining the physical address of the located page translation table; (3) locating a page directory by searching at least a subset of all physical memory for a page directory whose first entry corresponds to the physical address of the located page translation table; (4) determining the physical address of the located page directory; and (5) using the physical address of the located page directory as the value of the page directory base register.
Claim 2
Dependent Claim
190 words
In a computer system having: (a) a processing unit; (b) a memory circuit having addressable memory locations in circuit communication with the processing unit; and (c) a memory manager in circuit communication with the processing unit and the memory circuit, the memory manager having a page directory base register associated therewith for affecting accesses by the processing unit to the memory circuit and associating a linear address to a physical address of the memory locations in the memory circuit; a method of estimating the value of the page directory base register, comprising the steps of: (1) locating a page translation table by searching at least a subset of all physical memory for a page translation table; (2) determining the physical address of the located page translation table; (3) locating a page directory by searching at least a subset of all physical memory for a page directory whose first entry corresponds to the physical address of the located page translation table; (4) determining the physical address of the located page directory; and (5) using the physical address of the located page directory as the value of the page directory base register.
Claim 3
Dependent Claim
51 words
A method of determining the appropriate value of a page directory base register according to claim 1 wherein said step of searching the pages of physical memory for a page translation table comprises the step of comparing the value stored at a fixed offset into each page with a predetermined value.
Claim 4
Dependent Claim
151 words
In a computer system having: (a) a processing unit; (b) a memory circuit in circuit communication with the processing unit; and (c) a memory manager in circuit communication with the processing unit and the memory circuit, the memory manager having a page directory base register associated therewith for affecting accesses by the processing unit to the memory circuit and associating a linear address to a physical address of the memory locations in the memory circuit; a method of verifying an estimated value of the page directory base register, comprising the steps of: (1) estimating the value of the page directory base register; (2) determining a linear address associated with a known physical address; (3) determining a translated physical address using the estimated value of the page directory base register and the linear address associated with a known physical address; and (4) comparing the translated physical address to the known physical address.
Claim 5
Dependent Claim
151 words
In a computer system having: (a) a processing unit; (b) a memory circuit in circuit communication with the processing unit; and (c) a memory manager in circuit communication with the processing unit and the memory circuit, the memory manager having a page directory base register associated therewith for affecting accesses by the processing unit to the memory circuit and associating a linear address to a physical address of the memory locations in the memory circuit; a method of verifying an estimated value of the page directory base register, comprising the steps of: (1) estimating the value of the page directory base register; (2) determining a linear address associated with a known physical address; (3) determining a translated physical address using the estimated value of the page directory base register and the linear address associated with a known physical address; and (4) comparing the translated physical address to the known physical address.
Claim 6
Dependent Claim
46 words
A method of verifying an estimated value of the page directory base register according to claim 3 wherein said step of comparing the translated physical address to the known physical address comprises the step of verifying that the translated physical address is located in physical memory.
Claim 7
Dependent Claim
159 words
In a computer system having: (a) a processing unit; (b) a memory circuit in circuit communication with the processing unit; and (c) a memory manager in circuit communication with the processing unit and the memory circuit, the memory manager having a page directory base register associated therewith for affecting accesses by the processing unit to the memory circuit and associating a linear address to a physical address of the memory locations in the memory circuit; a method of verifying an estimated value of the page directory base register, comprising the steps of: (1) estimating the value of the page directory base register; (2) determining a linear address associated with a table having at least one known entry; (3) determining a translated physical address using the estimated value of the page directory base register and the linear address associated with the table having at least one known entry; and (4) comparing the translated physical address to the known table entry.
Claim 8
Dependent Claim
159 words
In a computer system having: (a) a processing unit; (b) a memory circuit in circuit communication with the processing unit; and (c) a memory manager in circuit communication with the processing unit and the memory circuit, the memory manager having a page directory base register associated therewith for affecting accesses by the processing unit to the memory circuit and associating a linear address to a physical address of the memory locations in the memory circuit; a method of verifying an estimated value of the page directory base register, comprising the steps of: (1) estimating the value of the page directory base register; (2) determining a linear address associated with a table having at least one known entry; (3) determining a translated physical address using the estimated value of the page directory base register and the linear address associated with the table having at least one known entry; and (4) comparing the translated physical address to the known table entry.
References Cited (Backward Citations)
US5239635A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-19 | 2000-05-20 | 2000-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-19 | 2004-05-20 | 2004-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-19 | 2008-05-20 | 2008-11-19 | $7700.00 | Window Closed / Lapsed |