Virtual address to physical address translation using page tables in virtual memory

Claim 2

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a contiguous page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing preselected portions of the page table memory space to provide corresponding physical address information to the translation mechanism; (h) a base virtual address register containing a base virtual address of a set of contiguous virtual addresses corresponding to the physical addresses used to reference the contiguous page table memory space of the physical address space; (i) a page table prototype register containing fixed offset information between a first physical address which locates the base of the contiguous page table memory space in the physical address space, and the base virtual address contained in the base virtual address register; (j) means for loading the translation buffer with the preselected portions of the page table memory space; (k) the means for loading the translation buffer being coupled to the central processing unit, the base virtual address register and the page table prototype register such that the means for loading the translation buffer: (i) adds a portion of a first virtual address generated by the central processing unit to the base virtual address contained in the base virtual address register to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) adds at least a portion of the second virtual address to the offset information contained in the page table prototype register to yield physical address information corresponding to the second virtual address, and (iii) loads the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.

Claim 3

The computer system of claim 1 wherein the means for loading the translation buffer operates to simulate a bypass of the translation mechanism by generating null mapping information, the null mapping information including at least a portion of a preselected virtual address and physical address information which is equal to the at least a portion of a preselected virtual address, and loading the null mapping information into the translation buffer in order to cause the translation mechanism to generate a physical address equal to the preselected virtual address when an address equal to the preselected virtual address is applied to the translation mechanism.

Claim 4

The computer system of claim 1 wherein (a) the virtual address space of the memory system is divided into pages, each of the pages being identified by a virtual page number and each of the pages including a predetermined number of addressable units of data, (b) the physical address space of the memory system is divided into page frames, each of the page frames being identified by a page frame number and each of the page frames including a number of addressable units of data equal to the predetermined number of addressable units of data contained in a page of the virtual address space, (c) the translation buffer containing the virtual page numbers for the preselected ones of the virtual addresses of the preselected portion of the data referenced by virtual addresses and the page frame numbers corresponding to the next beforementioned virtual page numbers, (d) said translation mechanism determining the physical addresses from the virtual addresses and the corresponding page frame numbers contained in the translation buffer.

Claim 5

The computer system of claim 3 wherein the page table prototype register contains a page frame number equal to a page frame number relating to the first physical address locating the base of the contiguous page table memory space minus a virtual page number relating to the base virtual address contained in the base virtual address register.

Claim 6

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing information identical to preselected portions of the page table memory space in order to provide corresponding physical address information to the translation mechanism; (h) the page table memory space further referenced by a set of virtual addresses, which correspond to the physical addresses, for referencing the page table memory space; (i) the translation buffer further including at least certain ones of the set of virtual addresses and the corresponding physical address to provide the translation mechanism with information to translate the at least certain ones of the virtual addresses to the corresponding physical addresses, for referencing the page table memory space; and (j) means for loading the translation buffer with the information identical to preselected portions of the page table memory space, said means coupled to the central processing unit and including a page table entry prototype mechanism such that said means for loading the translation buffer operates: (i) to add, in the page table prototype mechanism, a proton of a first virtual address generated by the central processing unit to a base virtual address of the set of virtual addresses corresponding to the physical addresses used to reference the page table memory space of the physical address space to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) to input the second virtual address into the page table prototype mechanism, which page table prototype mechanism contains known cross reference information between each virtual address of the set of virtual addresses and the corresponding physical address for referencing the page table memory space, and which page table entry prototype mechanism operates to generate physical address information corresponding to the second virtual address, and (iii) to load the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.

Claim 7

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing information identical to preselected portions of the page table memory space in order to provide corresponding physical address information to the translation mechanism; (h) the page table memory space further referenced by a set of virtual addresses, which correspond to the physical addresses, for referencing the page table memory space; (i) the translation buffer further including at least certain ones of the set of virtual addresses and the corresponding physical address to provide the translation mechanism with information to translate the at least certain ones of the virtual addresses to the corresponding physical addresses, for referencing the page table memory space; and (j) means for loading the translation buffer with the information identical to preselected portions of the page table memory space, said means coupled to the central processing unit and including a page table entry prototype mechanism such that said means for loading the translation buffer operates: (i) to add, in the page table prototype mechanism, a proton of a first virtual address generated by the central processing unit to a base virtual address of the set of virtual addresses corresponding to the physical addresses used to reference the page table memory space of the physical address space to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) to input the second virtual address into the page table prototype mechanism, which page table prototype mechanism contains known cross reference information between each virtual address of the set of virtual addresses and the corresponding physical address for referencing the page table memory space, and which page table entry prototype mechanism operates to generate physical address information corresponding to the second virtual address, and (iii) to load the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.

Claim 8

A computer system, which comprises: (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) certain ones of the virtual addresses each having a corresponding physical address; (d) the physical address space having a page table memory space therein; the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a certain page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing preselected portions of the page table memory space to provide corresponding physical address information to the translation mechanism; (h) the page table memory space further referenced by a set of virtual addresses which correspond to the physical addresses for referencing the page table memory space; (i) a page table prototype mechanism including known cross reference information between the set of virtual addresses and the corresponding physical addresses for referencing the page table memory space, the known cross-reference information comprising offset information between all virtual addresses and their corresponding physical addresses; (j) said page table prototype mechanism operating to determine physical address information for referencing the page table memory space from a corresponding one of the set of virtual addresses and the known cross reference information contained in the page table prototype mechanism.

Claim 9

A computer system, which comprises: (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) certain ones of the virtual addresses each having a corresponding physical address; (d) the physical address space having a page table memory space therein; the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a certain page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing preselected portions of the page table memory space to provide corresponding physical address information to the translation mechanism; (h) the page table memory space further referenced by a set of virtual addresses which correspond to the physical addresses for referencing the page table memory space; (i) a page table prototype mechanism including known cross reference information between the set of virtual addresses and the corresponding physical addresses for referencing the page table memory space, the known cross-reference information comprising offset information between all virtual addresses and their corresponding physical addresses; (j) said page table prototype mechanism operating to determine physical address information for referencing the page table memory space from a corresponding one of the set of virtual addresses and the known cross reference information contained in the page table prototype mechanism.

Claim 10

The computer system of claim 6, wherein: (a) the page table memory space occupies contiguous locations in both the physical address space and the virtual address space; and (b) the offset information comprising fixed offset information.

Claim 13

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a contiguous page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing preselected portions of the page table memory space to provide corresponding physical address information to the translation mechanism; (h) a base virtual address register containing a base virtual address of a set of contiguous virtual addresses corresponding to the physical addresses used to reference the contiguous page table memory space of the physical address space; (i) a page table prototype register containing fixed offset information between a first physical address which locates the base of the contiguous page table memory space in the physical address space, and the base virtual address contained in the base virtual address register; (j) the central processing unit including means for loading the translation buffer with the preselected portions of the page table memory space; (k) the means for loading the translation buffer being coupled to the base virtual address register and the page table prototype register such that the means for loading the translation buffer: (i) adds a portion of a first virtual address generated by the central processing unit to the base virtual address contained in the base virtual address register to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) adds at least a portion of the second virtual address to the offset information contained in the page table prototype register to yield physical address information corresponding to the second virtual address, and (iii) loads the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.

Claim 14

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a contiguous page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing preselected portions of the page table memory space to provide corresponding physical address information to the translation mechanism; (h) a base virtual address register containing a base virtual address of a set of contiguous virtual addresses corresponding to the physical addresses used to reference the contiguous page table memory space of the physical address space; (i) a page table prototype register containing fixed offset information between a first physical address which locates the base of the contiguous page table memory space in the physical address space, and the base virtual address contained in the base virtual address register; (j) the central processing unit including means for loading the translation buffer with the preselected portions of the page table memory space; (k) the means for loading the translation buffer being coupled to the base virtual address register and the page table prototype register such that the means for loading the translation buffer: (i) adds a portion of a first virtual address generated by the central processing unit to the base virtual address contained in the base virtual address register to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) adds at least a portion of the second virtual address to the offset information contained in the page table prototype register to yield physical address information corresponding to the second virtual address, and (iii) loads the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.

Claim 15

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing information identical to preselected portions of the page table memory space in order to provide corresponding physical address information to the translation mechanism; (h) a page table memory space further referenced by a set of virtual addresses, which correspond to the physical addresses, for referencing the page table memory space; (i) the translation buffer further including at least certain ones of the set of virtual addresses and the corresponding physical addresses to provide the translation mechanism with information to translate the at least certain ones of the virtual addresses to the corresponding physical addresses, for referencing the page table memory space; and (j) the central processing unit including means for loading the translation buffer with the information identical to preselected portions of the page table memory space, said means including a page table entry prototype mechanism such that said means for loading the translation buffer operates: (i) to add, in the page table prototype mechanism, a portion of a first virtual address generated by the central processing unit to a base virtual address of the set of virtual addresses corresponding to the physical addresses used to reference the page table memory space of the physical address space to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) to input the second virtual address into the page table prototype mechanism, which page table prototype mechanism contains known cross reference information between each virtual address of the set of virtual addresses and the corresponding physical address for referencing the page table memory space, and which page table entry prototype mechanism operates to generate physical address information corresponding to the second virtual address, and (iii) to load the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.

Claim 16

A computer system, which comprises (a) a central processing unit; (b) a memory system having a virtual address space containing data referenced by a plurality of virtual addresses and a physical address space containing data referenced by a plurality of physical addresses; (c) the data in the physical address space, referenced by the physical addresses, comprising a preselected portion of the data in the virtual address space referenced by the virtual addresses such that the virtual addresses, of the preselected portion of data referenced by virtual addresses, have corresponding physical addresses; (d) the physical address space also having a page table memory space therein, the page table memory space being referenced by physical addresses which locate locations in the page table memory space, each of the locations containing at least a page table entry for a preselected page of the virtual address space; (e) a translation mechanism for translating virtual addresses generated by the central processing unit to corresponding physical addresses; (f) said translation mechanism being coupled between the central processing unit and the memory system such that the virtual addresses generated by the central processing unit are translated to the corresponding physical addresses, which corresponding physical addresses are transmitted to the physical address space of the memory system to fetch data referenced by the physical addresses; (g) said translation mechanism including a translation buffer containing information identical to preselected portions of the page table memory space in order to provide corresponding physical address information to the translation mechanism; (h) a page table memory space further referenced by a set of virtual addresses, which correspond to the physical addresses, for referencing the page table memory space; (i) the translation buffer further including at least certain ones of the set of virtual addresses and the corresponding physical addresses to provide the translation mechanism with information to translate the at least certain ones of the virtual addresses to the corresponding physical addresses, for referencing the page table memory space; and (j) the central processing unit including means for loading the translation buffer with the information identical to preselected portions of the page table memory space, said means including a page table entry prototype mechanism such that said means for loading the translation buffer operates: (i) to add, in the page table prototype mechanism, a portion of a first virtual address generated by the central processing unit to a base virtual address of the set of virtual addresses corresponding to the physical addresses used to reference the page table memory space of the physical address space to yield a second virtual address for a page table memory space location containing the corresponding physical address information for the first virtual address, (ii) to input the second virtual address into the page table prototype mechanism, which page table prototype mechanism contains known cross reference information between each virtual address of the set of virtual addresses and the corresponding physical address for referencing the page table memory space, and which page table entry prototype mechanism operates to generate physical address information corresponding to the second virtual address, and (iii) to load the translation buffer with at least a portion of the second virtual address and the physical address information corresponding to the second virtual address.