US5577080A
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Digital phase-locked loop circuit with filter coefficient generator
Assignee: Toshiba Corp
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Filing: 1994-02-25
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Granted: 1996-11-19
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Expires: 2014-02-25
Abstract
Abstract A digital phase-locked loop (DPLL) circuit, which achieves a high-precise phase matching between input and output clocks at high speed, irrespective of phase difference between both, is disclosed. The DPLL has a phase comparator for sequentially comparing an input clock with an output clock in phase and outputting phase comparison result signals; a random walk filter for sequentially adding and accumulating the comparison result signals inputted by the phase comparator, discriminating a relative magnitude between the obtained addition data and threshold value information, and outputting a frequency change signal corresponding to the discriminated result and the phase shift amount information; a variable frequency oscillator for generating the output clock and changing frequency of the output clock according to the frequency change signal; and a filter coefficient generating circuit for changing and outputting at least one of the outputted threshold value information and the phase shift amount information according to the phase synchronous status supplied from an operation status detecting circuit.
Inventors
- 👤 Kenji Sakaue
- 👤 Koji Ogura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:45
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0992; H03L7/0993; H03L7/085; H03L7/091; H03L7/10; H03L7/107; H03L7/1075
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
333 words
A digital phase-locked loop circuit, operable with an oscillator signal, for generating an output clock and for synchronizing the output clock with an input clock by shifting phase of the output clock, the digital phase-locked loop circuit comprising: phase comparing means for sequentially comparing the input clock with the output clock in phase and outputting comparison result signals; a random walk filter having: an accumulation section for sequentially adding and accumulating the comparison result signals supplied from said phase comparing means and outputting the added and accumulated data as addition data; a discrimination section, responsive to a threshold value information signal, for discriminating a relative magnitude between the addition data supplied from said accumulation section and outputting a discriminated result; and a frequency change signal generating section, responsive to a phase shift amount information signal, for outputting a frequency change signal based on the phase shift amount information signal and the discriminated result inputted by said discrimination section; oscillating means for generating the output clock and an internal clock signal and for changing frequency of the output clock according to the frequency change signal supplied from said random walk filter, wherein the internal clock signal represents a subdivision of the oscillator signal; filter coefficient generating means, responsive to an operation mode signal, for outputting the threshold value information signal to the discrimination section and for outputting the phase shift amount information signal to the frequency change signal generating section, so that at least one of the outputted threshold value information signal and the phase shift amount information signal is changed according to the operation mode signal, wherein the threshold value information signal and the phase shift amount information signal are prestored in the filter coefficient generating means and are selected in response to the operator mode signal; and operation status detecting means, responsive to a change in amplitude of the input clock and the internal clock signal from the oscillating means, for outputting the operation mode signal to the filter coefficient generating means.
Claim 2
Dependent Claim
333 words
A digital phase-locked loop circuit, operable with an oscillator signal, for generating an output clock and for synchronizing the output clock with an input clock by shifting phase of the output clock, the digital phase-locked loop circuit comprising: phase comparing means for sequentially comparing the input clock with the output clock in phase and outputting comparison result signals; a random walk filter having: an accumulation section for sequentially adding and accumulating the comparison result signals supplied from said phase comparing means and outputting the added and accumulated data as addition data; a discrimination section, responsive to a threshold value information signal, for discriminating a relative magnitude between the addition data supplied from said accumulation section and outputting a discriminated result; and a frequency change signal generating section, responsive to a phase shift amount information signal, for outputting a frequency change signal based on the phase shift amount information signal and the discriminated result inputted by said discrimination section; oscillating means for generating the output clock and an internal clock signal and for changing frequency of the output clock according to the frequency change signal supplied from said random walk filter, wherein the internal clock signal represents a subdivision of the oscillator signal; filter coefficient generating means, responsive to an operation mode signal, for outputting the threshold value information signal to the discrimination section and for outputting the phase shift amount information signal to the frequency change signal generating section, so that at least one of the outputted threshold value information signal and the phase shift amount information signal is changed according to the operation mode signal, wherein the threshold value information signal and the phase shift amount information signal are prestored in the filter coefficient generating means and are selected in response to the operator mode signal; and operation status detecting means, responsive to a change in amplitude of the input clock and the internal clock signal from the oscillating means, for outputting the operation mode signal to the filter coefficient generating means.
Claim 3
Dependent Claim
75 words
The digital phase-locked loop circuit according to claim 1, wherein said filter coefficient generating means has means for changing and outputting the threshold value information signal in such a way that a threshold value is determined to be small when a phase difference between the input and output clocks is larger than a predetermined value, but to be large when the phase difference between the input and output clocks is smaller than the predetermined value.
Claim 4
Dependent Claim
77 words
The digital phase-locked loop circuit according to claim 1, wherein said filter coefficient generating means has means for changing and outputting the phase shift amount information signal in such a way that a phase shift amount is determined to be large when a phase difference between the input and output clocks is larger than a predetermined value, but to be small when the phase difference between the input and output clocks is smaller than the predetermined value.
Claim 5
Dependent Claim
69 words
The digital phase-locked loop circuit according to claim 1, wherein said filter coefficient generating means has means for changing and outputting the threshold value information signal in such a way that a threshold value is determined to be small within a predetermined time period after an initiation of a phase synchronous operation of the input and output clocks, but to be large after the predetermined time period has elapsed.
Claim 6
Dependent Claim
44 words
The digital phase-locked loop circuit of claim 4, which further comprises operation status detecting means for detecting a start of the synchronous operation on the basis of change in amplitude of the input clock and outputting a detected signal to said filer detecting means.
Claim 7
Dependent Claim
69 words
The digital phase-locked loop circuit according to claim 1, wherein said filter coefficient generating means has means for changing and outputting the phase shift amount information signal in such a way that a phase shift amount is determined to be large within a predetermined time period after the phase synchronous operation between the input and output clocks starts, but to be small after the predetermined time period has elapsed.
Claim 8
Dependent Claim
44 words
The digital phase-locked loop circuit of claim 6, which further comprises operation status detecting means for detecting a start of the synchronous operation on the basis of change in amplitude of the input clock and outputting a detected signal to said filer detecting means.
Claim 9
Dependent Claim
50 words
The digital phase-locked loop circuit according to claim 1, wherein said operating mode signal of said operation status detecting means represents a transition from an intermittent reception mode to a continuous operation mode after the elapse of a predetermined time from the detection of a start of a synchronous operation.
Claim 10
Dependent Claim
101 words
The digital phase-locked loop circuit according to claim 8, wherein the threshold value information signal from the filter coefficient generating means includes a small threshold value, and the phase shift amount information signal from the filter coefficient generating means includes a large phase shift amount when a phase difference between the input and output clocks is larger than a predetermined value, and the threshold value information signal includes a large threshold value, and the phase shift amount information signal includes a small phase shift amount when the phase difference between the input and output clocks is smaller than the predetermined value.
Claim 11
Dependent Claim
272 words
A digital phase-locked loop circuit, operable with an oscillator signal and an external control signal, for generating an output clock and for synchronizing the output clock with an input clock by shifting phase of the output clock, the digital phase-locked loop circuit comprising: phase comparing means for sequentially comparing the input clock with the output clock in phase and outputting comparison result signals; a random walk filter having: an accumulation section for sequentially adding and accumulating the comparison result signals supplied from said phase comparing means and outputting the added and accumulated data as addition data; a discrimination section, responsive to a threshold value information signal, for discriminating a relative magnitude between the addition data supplied from said accumulation section and outputting a discriminated result; and a frequency change signal generating section, responsive to a phase shift amount information signal, for outputting a frequency change signal based on the phase shift amount information signal and the discriminated result supplied from said discrimination section; oscillating means for generating the output clock and an internal clock signal and for changing frequency of the output clock according to the frequency change signal supplied from said random walk filter, wherein the internal clock signal represents a subdivision of the oscillator signal; filter coefficient generating means, responsive to the external control signal, for outputting the threshold value information signal to the discrimination section and for outputting the phase shift amount information signal to the frequency change signal generating section, so that at least one of the outputted threshold value information signal and the phase shift amount information signal is changed in response to the external control signal.
Claim 12
Dependent Claim
272 words
A digital phase-locked loop circuit, operable with an oscillator signal and an external control signal, for generating an output clock and for synchronizing the output clock with an input clock by shifting phase of the output clock, the digital phase-locked loop circuit comprising: phase comparing means for sequentially comparing the input clock with the output clock in phase and outputting comparison result signals; a random walk filter having: an accumulation section for sequentially adding and accumulating the comparison result signals supplied from said phase comparing means and outputting the added and accumulated data as addition data; a discrimination section, responsive to a threshold value information signal, for discriminating a relative magnitude between the addition data supplied from said accumulation section and outputting a discriminated result; and a frequency change signal generating section, responsive to a phase shift amount information signal, for outputting a frequency change signal based on the phase shift amount information signal and the discriminated result supplied from said discrimination section; oscillating means for generating the output clock and an internal clock signal and for changing frequency of the output clock according to the frequency change signal supplied from said random walk filter, wherein the internal clock signal represents a subdivision of the oscillator signal; filter coefficient generating means, responsive to the external control signal, for outputting the threshold value information signal to the discrimination section and for outputting the phase shift amount information signal to the frequency change signal generating section, so that at least one of the outputted threshold value information signal and the phase shift amount information signal is changed in response to the external control signal.
Claim 13
Dependent Claim
27 words
The digital phase-locked loop circuit according to claim 10, wherein the external control signal for controlling the filter coefficient generating means is generated from an external processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-19 | 2000-05-20 | 2000-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-19 | 2004-05-20 | 2004-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-19 | 2008-05-20 | 2008-11-19 | $7700.00 | Window Closed / Lapsed |