Symbol timing reproducing circuit

Abstract

Abstract PURPOSE:To shorten a pull-in time and to simultaneously reduce cycle skip probability and normal phase jitter by changing the ratio of frequency division deciding the inertia of a digital phase locked loop(DPLL) and the number of steps of a random walk filter(RWF) in multiple stages according to the advancement of a pull-in operation. CONSTITUTION:The phase is pulled in at high speed up to near the optimum phase in the state of reducing the inertia of the DPLL by a phase comparator 4, up/down counter 5 and comparator 6. At such a time, the comparator 6 calculates phase correction to a variable frequency divider 3 according to the over-flow signal or the under-flow signal and simultaneously resets the counter 5 at the central value. Each time this number of times exceeds a value (m) set to a mode controller 7, the synchronization of symbol timing is held by enlarging the inertia of the DPLL through each mode enlarging either the threshold value of the comparator 6 or the DPLL frequency division ratio of the variable frequency divider 3. Thus, the sufficiently reduced normal phase jitter and cycle skip probability can be realized in the short pull-in time.

Inventors

• 👤 Yasuyuki Oishi
• 👤 泰之 大石
• 👤 Eisuke Fukuda
• 👤 英輔 福田
• 👤 Takeshi Takano
• 👤 健 高野

Bibliographic Details