Phase comparing circuit and PLL circuit

Claim 2

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal, the second control signal representing a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal; and fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and the second control signal generated by the third means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 3

The phase comparing circuit of claim 1, wherein the fourth means comprises a charge pump circuit.

Claim 4

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means for generating a second control signal in response to the clock signal, the second control signal representing a time interval between the first strobe point of the clock signal and a second strobe point of the clock signal which immediately follows the first strobe point of the clock signal; fourth means for generating a third control signal in response to the clock signal, the third control signal representing a time interval being equal to a half of a period of the clock signal and starting from the second strobe point of the clock signal; and fifth means connected to the second means, the third means, and the fourth means for generating a phase error signal in response to the first control signal generated by the second means, the second control signal generated by the third means, and the third control signal generated by the fourth means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 5

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means for generating a second control signal in response to the clock signal, the second control signal representing a time interval between the first strobe point of the clock signal and a second strobe point of the clock signal which immediately follows the first strobe point of the clock signal; fourth means for generating a third control signal in response to the clock signal, the third control signal representing a time interval being equal to a half of a period of the clock signal and starting from the second strobe point of the clock signal; and fifth means connected to the second means, the third means, and the fourth means for generating a phase error signal in response to the first control signal generated by the second means, the second control signal generated by the third means, and the third control signal generated by the fourth means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 6

The phase comparing circuit of claim 3, wherein the first means comprises a plurality of signal detectors generating different detection signals in response to the multi-level signal respectively, the detection signals representing whether or not the multi-level signal is in different given levels respectively, and wherein the second means is responsive to the detection signals generated by the signal detectors.

Claim 7

The phase comparing circuit of claim 3, wherein the fifth means comprises a charge pump circuit.

Claim 8

A Phase locked loop circuit comprising the phase comparing circuit of claim 3.

Claim 9

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal in cases where a trailing edge of the pulse in the detection signal precedes a second strobe point of the clock signal which immediately follows the first strobe point of the clock signal, and for generating a third control signal and a fourth control signal in response to the clock signal in cases where the second strobe point of the clock signal precedes the trailing edge of the pulse in the detection signal, the second control signal representing a time interval between the first strobe point of the clock signal and the trailing edge of the pulse in the detection signal, the third control signal representing a time interval between the first strobe point of the clock signal and the second strobe point of the clock signal, the fourth control signal representing a time interval equal to a half of a period of the clock signal which starts from the second strobe point of the clock signal; and fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and the second control signal generated by the third means or in response to the first control signal generated by the second means and the third and fourth control signals generated by the third means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 10

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal in cases where a trailing edge of the pulse in the detection signal precedes a second strobe point of the clock signal which immediately follows the first strobe point of the clock signal, and for generating a third control signal and a fourth control signal in response to the clock signal in cases where the second strobe point of the clock signal precedes the trailing edge of the pulse in the detection signal, the second control signal representing a time interval between the first strobe point of the clock signal and the trailing edge of the pulse in the detection signal, the third control signal representing a time interval between the first strobe point of the clock signal and the second strobe point of the clock signal, the fourth control signal representing a time interval equal to a half of a period of the clock signal which starts from the second strobe point of the clock signal; and fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and the second control signal generated by the third means or in response to the first control signal generated by the second means and the third and fourth control signals generated by the third means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 11

The phase comparing circuit of claim 7, wherein the first means comprises a plurality of signal detectors generating different detection signals in response to the multi-level signal respectively, the detection signals representing whether or not the multi-level signal is in different given levels respectively, and wherein the second means and the third means are responsive to the detection signals generated by the signal detectors.

Claim 12

The phase comparing circuit of claim 7, wherein the fourth means comprises a charge pump circuit.

Claim 13

A Phase locked loop circuit comprising the phase comparing circuit of claim 7.

Claim 14

A phase comparing circuit comprising: a) a plurality of signal detectors generating different detection signals in response to a multi-level signal respectively, the detection signals representing whether or not the multi-level signal is in different given levels respectively; and b) a plurality of phase comparing sections following the signal detectors respectively and processing the detection signals generated by the signal detectors respectively; wherein each of the phase comparing sections comprises: b1) first means for generating a first control signal in response to the related detection signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a strobe point of a clock signal which immediately follows the leading edge of the pulse in the detection signal; b2) second means for generating a second control signal in response to the related detection signal, the second control signal representing a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal; and b3) third means connected to the first means and the second means for generating a phase error signal in response to the first control signal generated by the first means and the second control signal generated by the second means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 15

A phase comparing circuit comprising: a) a plurality of signal detectors generating different detection signals in response to a multi-level signal respectively, the detection signals representing whether or not the multi-level signal is in different given levels respectively; and b) a plurality of phase comparing sections following the signal detectors respectively and processing the detection signals generated by the signal detectors respectively; wherein each of the phase comparing sections comprises: b1) first means for generating a first control signal in response to the related detection signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a strobe point of a clock signal which immediately follows the leading edge of the pulse in the detection signal; b2) second means for generating a second control signal in response to the related detection signal, the second control signal representing a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal; and b3) third means connected to the first means and the second means for generating a phase error signal in response to the first control signal generated by the first means and the second control signal generated by the second means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 16

A Phase locked loop circuit comprising: first means for generating a clock signal; second means connected to the first means for generating a first control signal in response to an input signal and the clock signal generated by the first means, the first control signal representing a time interval between a leading edge of a pulse in the input signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the input signal; third means connected to the first means for generating a second control signal in response to the clock signal generated by the first means and the input signal, the second control signal representing a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the input signal; fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and the second control signal generated by the third means, the phase error signal representing a difference between a phase of the clock signal generated by the first means and a phase of the input signal; and fifth means for controlling the phase of the clock signal in response to the phase error signal generated by the fourth means.

Claim 17

A Phase locked loop circuit comprising: first means for generating a clock signal; second means connected to the first means for generating a first control signal in response to an input signal and the clock signal generated by the first means, the first control signal representing a time interval between a leading edge of a pulse in the input signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the input signal; third means connected to the first means for generating a second control signal in response to the clock signal generated by the first means and the input signal, the second control signal representing a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the input signal; fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and the second control signal generated by the third means, the phase error signal representing a difference between a phase of the clock signal generated by the first means and a phase of the input signal; and fifth means for controlling the phase of the clock signal in response to the phase error signal generated by the fourth means.

Claim 18

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal in cases where a trailing edge of the pulse in the detection signal precedes a second strobe point of the clock signal which immediately follows the first strobe point of the clock signal, and for generating a third control signal and a fourth control signal in response to the detection signal generated by the first means and the clock signal in cases where the second strobe point of the clock signal precedes the trailing edge of the pulse in the detection signal, the second control signal representing a time interval between the first strobe point of the clock signal and the trailing edge of the pulse in the detection signal, the third control signal representing a time interval between the first strobe point of the clock signal and the second strobe point of the clock signal, the fourth control signal representing a time interval between the trailing edge of the pulse in the detection signal and a third strobe point of the clock signal which immediately follows the trailing edge of the pulse in the detection signal; and fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and one of (1) the second control signal generated by the third means and (2) a combination of the third and fourth control signals generated by the third means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 19

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal in cases where a trailing edge of the pulse in the detection signal precedes a second strobe point of the clock signal which immediately follows the first strobe point of the clock signal, and for generating a third control signal and a fourth control signal in response to the detection signal generated by the first means and the clock signal in cases where the second strobe point of the clock signal precedes the trailing edge of the pulse in the detection signal, the second control signal representing a time interval between the first strobe point of the clock signal and the trailing edge of the pulse in the detection signal, the third control signal representing a time interval between the first strobe point of the clock signal and the second strobe point of the clock signal, the fourth control signal representing a time interval between the trailing edge of the pulse in the detection signal and a third strobe point of the clock signal which immediately follows the trailing edge of the pulse in the detection signal; and fourth means connected to the second means and the third means for generating a phase error signal in response to the first control signal generated by the second means and one of (1) the second control signal generated by the third means and (2) a combination of the third and fourth control signals generated by the third means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 20

The phase comparing circuit of claim 13, wherein the first means comprises a plurality of signal detectors generating different detection signals in response to the multi-level signal respectively, the detection signals representing whether or not the multi-level signal is in different given levels respectively, and wherein the second means and the third means are responsive to the detection signals generated by the signal detectors.

Claim 21

The phase comparing circuit of claim 13, wherein the fourth means comprises a charge pump circuit.

Claim 22

A Phase locked loop circuit comprising the phase comparing circuit of claim 13.

Claim 23

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal, the second control signal representing a time interval between a trailing edge of the pulse in the detection signal and a second strobe point of the clock signal which immediately follows the trailing edge of the pulse in the detection signal; fourth means for generating a third control signal in response to the clock signal, the third control signal representing a time interval equal to a period of the clock signal; and fifth means connected to the second means, the third means, and the fourth means for generating a phase error signal in response to the first control signal generated by the second means, the second control signal generated by the third means, and the third control signal generated by the fourth means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 24

A phase comparing circuit comprising: first means for generating a detection signal in response to a multi-level signal, the detection signal representing whether or not the multi-level signal is in a given level; second means connected to the first means for generating a first control signal in response to the detection signal generated by the first means and a clock signal, the first control signal representing a time interval between a leading edge of a pulse in the detection signal and a first strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal; third means connected to the first means for generating a second control signal in response to the detection signal generated by the first means and the clock signal, the second control signal representing a time interval between a trailing edge of the pulse in the detection signal and a second strobe point of the clock signal which immediately follows the trailing edge of the pulse in the detection signal; fourth means for generating a third control signal in response to the clock signal, the third control signal representing a time interval equal to a period of the clock signal; and fifth means connected to the second means, the third means, and the fourth means for generating a phase error signal in response to the first control signal generated by the second means, the second control signal generated by the third means, and the third control signal generated by the fourth means, the phase error signal representing a difference between a phase of the detection signal generated by the first means and a phase of the clock signal.

Claim 25

The phase comparing circuit of claim 17, wherein the first means comprises a plurality of signal detectors generating different detection signals in response to the multi-level signal respectively, the detection signals representing whether or not the multi-level signal is in different given levels respectively, and wherein the second means and the third means are responsive to the detection signals generated by the signal detectors.

Claim 26

The phase comparing circuit of claim 17, wherein the fifth means comprises a charge pump circuit.

Claim 27

A Phase locked loop circuit comprising the phase comparing circuit of claim 17.