EP0530776A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Timing recovering apparatus and automatic slice apparatus including the same
Assignee: Panasonic Holdings Corp
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Filing: 1992-09-02
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Granted: —
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Expires: 2012-09-02
Abstract
Abstract A timing recovering apparatus comprises an equalizer for equalizing a digital data signal subjected to interleaved NRZI such that the digital data signal has partial response (1, 0, -1), two comparators for comparing the equalized data signal with two different reference levels, two phase comparing portions for detecting phase difference between the outputs of the comparators and a reproduced clock signal separately, an adder for summing the outputs of the phase comparators, and a VCO for generating the reproduce clock signal in accordance with the output of the adder. This timing recovering apparatus performs phase comparing with two different phase comparators and PLL control is performed sum of the output of the two different phase comparators, so that the clock signal is not affected by data pattern of the data signal. An automatic slice apparatus comprises the equalizer for equalizing a digital data signal subjected to interleaved NRZI, and two comparators supplied with reference levels, and the timing recovering apparatus, detects amplitude of the output of the equalizer in response to the reproduced clock signal to compensate the reference levels.
Inventors
- 👤 Masafumi Shimotashiro
- 👤 Kiyokazu Hashimoto
- 👤 Yoshio Higashida
- 👤 Koichi Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:05
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10055; G11B20/14; G11B20/1403
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
184 words
A timing recovering apparatus comprising: (a) equalizing means for equalizing a digital data signal such that said digital data signal has partial response (1, 0, -1); (b) first and second comparing means for comparing an output of said equalizing means with first and second reference levels respectively, said first and second reference levels being different from each other; (c) first and second clock signal shaping means for shaping outputs of said first and second comparing means respectively; (d) first phase comparing means for detecting phase difference between a reproduced clock signal with an output of said first clock signal shaping means; (e) second phase comparing means for detecting phase difference between said reproduced clock signal with an output of said second clock signal shaping means; (f) adding means for adding an output of said first phase comparing means to an output of said second phase comparing means; (g) low-pass filter means for low-pass filtering an output of said adding means; and (h) oscillation means for generating said reproduced clock signal with frequency thereof controlled in accordance with an output of said low-pass filter means.
Claim 2
Dependent Claim
66 words
A timing recovering apparatus as claimed in claim 1, wherein said first clock signal shaping means comprises delay means for delaying said output of said first comparing means by half of a period of a clock signal of said data signal to be reproduced and Exclusive-OR operation means for Exclusive-OR operating between said output of said first comparing means and an output of said delay means.
Claim 3
Dependent Claim
66 words
A timing recovering apparatus as claimed in claim 1, wherein said second clock signal shaping means comprises delay means for delaying said output of said second comparing means by half of a period of a clock signal of said data signal to be reproduced and Exclusive-OR operation means for Exclusive-OR operating between said output of said second comparing means and an output of said delay means.
Claim 4
Dependent Claim
163 words
A timing recovering apparatus comprising: (a) equalizing means for equalizing a digital data signal such that said digital data signal has partial response (1, 0, -1); (b) first and second comparing means for comparing an output of said equalizing means with first and second reference levels respectively, said first and second reference levels being different from each other; (c) first and second clock signal shaping means for shaping outputs of said first and second comparing means respectively; (d) adding means for linearly adding an output of said first clock signal shaping means to an output of said second clock signal shaping means; (e) phase comparing means, comprising an analog multiplier, for detecting phase difference between a reproduced clock signal with an output of said adding means; (f) low-pass filter means for low-pass filtering an output of said adding means; and (g) oscillation means for generating said reproduced clock signal with frequency thereof controlled in accordance with an output of said low-pass filter means.
Claim 5
Dependent Claim
64 words
A timing recovering apparatus as claimed in claim 4, wherein said first clock signal shaping means comprises delay means for delaying said output of said first comparing means by half of a period of a clock signal of said data signal to be reproduced and an analog multiplier for multiplying said output of said first comparing means and an output of said delay means.
Claim 6
Dependent Claim
64 words
A timing recovering apparatus as claimed in claim 4, wherein said second clock signal shaping means comprises delay means for delaying said output of said second comparing means by half of a period of a clock signal of said data signal to be reproduced and an analog multiplier for multiplying said output of said second comparing means and an output of said delay means.
Claim 7
Dependent Claim
166 words
An automatic slice apparatus comprising, (a) equalizing means for equalizing a digital data signal such that said digital data signal has partial response (1- 0, -1); (b) first and second comparing means for comparing an output of said equalizing means with first and second reference levels respectively, said first and second reference levels being different from each other; (c) timing recovering means responsive to outputs of said first and second comparing means for generating a clock signal with time base of said data signal recovered; (d) first and second data sampling means for sampling said output of said first and second comparing means respectively; (e) subtracting means for subtracting an output of second data sampling means from an output of said first data sampling means; and (f) multiplying means for multiplying an output of said equalizing means by an output of said subtracting means; and (g) level generating means for generating said first and second reference levels in accordance with an output of said multiplying means.
Claim 8
Dependent Claim
46 words
An automatic slice apparatus as claimed in claim 7, further comprising an automatic gain control circuit for amplifying said data signal with gain controlled in accordance with said output of said multiplying means, said data signal amplified by the same being supplied to said equalizing means.
References Cited (Backward Citations)
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