Patent US5576983A successfully refreshed from Google Patents.
US5576983A
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Arithmetic circuit for adaptive equalizer of LMS algorithm of reduced amount of operation
Assignee: NEC Electronics Corp
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Filing: 1994-12-22
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Granted: 1996-11-19
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Expires: 2014-12-22
Abstract
Abstract An arithmetic circuit for adaptive equalizer of Least Mean Square (LMS) algorithm. Includes a real operation part computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and computing a second product between an imaginary part signal of the data sequence and a product of an imaginary part signal of the error sequence and a step coefficient. Either of the first and second products is negative. The real operation part further computes a real part of an adaptation coefficient from the first and second products. An imaginary operation part computes a third product between the imaginary part signal of the data sequence and a product of the real part signal of the error sequence and the step coefficient, and computes a fourth product between the real part signal of the data sequence and a product of the imaginary part signal of the error sequence and the step coefficient, so as to obtain an imaginary part of an adaptation coefficient from the third and fourth products.
Inventors
- 👤 Toshimichi Shiokawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:50
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
An arithmetic circuit for adaptive equalizer of Least Mean Square (LMS) algorithm comprising: real operation means for computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and for computing a second product between an imaginary part signal of said data sequence and a product of an imaginary part signal of said error sequence and a step coefficient, wherein when either of said first and second products is negative, said real operation means obtains a real part of an adaptation coefficient from said first and second products; and imaginary operation means for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said step coefficient, and for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said step coefficient, wherein said imaginary operation means obtains an imaginary part of an adaptation coefficient from said third and fourth products.
Claim 2
Dependent Claim
190 words
An arithmetic circuit for adaptive equalizer of Least Mean Square (LMS) algorithm comprising: real operation means for computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and for computing a second product between an imaginary part signal of said data sequence and a product of an imaginary part signal of said error sequence and a step coefficient, wherein when either of said first and second products is negative, said real operation means obtains a real part of an adaptation coefficient from said first and second products; and imaginary operation means for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said step coefficient, and for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said step coefficient, wherein said imaginary operation means obtains an imaginary part of an adaptation coefficient from said third and fourth products.
Claim 3
Dependent Claim
210 words
An arithmetic circuit as claimed in claim 1, wherein said real operation means comprises: a first multiplier for computing a first product between said real part signal of said data sequence and a product of said real part signal of said error sequence and a positive step coefficient, a second multiplier for computing a second product between said imaginary part signal of said data sequence and a product of said imaginary part signal of said error sequence and a negative step coefficient, and a first subtracter for subtracting said second product from said first product so as to obtain said real part of said adaptation coefficient; and wherein said imaginary operation means comprises: a third multiplier for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said positive step coefficient, a fourth multiplier for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a second subtracter for subtracting said fourth product from third product so as to obtain said imaginary part of said adaptation coefficient from said third and fourth products.
Claim 4
Dependent Claim
211 words
An arithmetic circuit as claimed in claim 1, wherein said real operation means comprises: a first multiplier for computing a first product between an inverted real part signal of said data sequence and a product of said real part signal of said error sequence and a positive step coefficient, a second multiplier for computing a second product between said imaginary part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a first subtracter for subtracting said first product from said second product so as to obtain said real part of said adaptation coefficient; and wherein said imaginary operation means comprises: a third multiplier for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said positive step coefficient, a fourth multiplier for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a second subtracter for subtracting said fourth product from third product so as to obtain said imaginary part of said adaptation coefficient from said third and fourth products.
Claim 5
Dependent Claim
214 words
An arithmetic circuit as claimed in claim 1, wherein said real operation means comprises: a first multiplier for computing a first product between said real part signal of said data sequence and a product of said real part signal of said error sequence and a negative step coefficient, a second multiplier for computing a second product between said imaginary part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a first subtracter for subtracting said first product from said second product so as to obtain said real part of said adaptation coefficient; and wherein said imaginary operation means comprises: a third multiplier for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said positive step coefficient, a fourth multiplier for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a second subtracter or subtracting said fourth product from an output of said third product so as to obtain said imaginary part of said adaptation coefficient from said third and fourth products.
Claim 6
Dependent Claim
210 words
An arithmetic circuit as claimed in claim 1, wherein said real operation means comprises: a first multiplier for computing a first product between said real part signal of said data sequence and product of said real part signal of said error sequence and a positive step coefficient, a second multiplier for computing a second product between an inverted imaginary part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a first subtracter for subtracting said second product from said first product so as to obtain said real part of said adaptation coefficient; and wherein said imaginary operation means comprises a third multiplier for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said positive step coefficient, a fourth multiplier for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said positive step coefficient, and a second subtracter for subtracting said fourth product from third product so as to obtain said imaginary part of said adaptation coefficient from said third and fourth products.
Claim 7
Dependent Claim
181 words
An arithmetic circuit, comprising: real operation means for computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and for computing a second product between an imaginary part signal of said data sequence and a product of an imaginary part signal of said error sequence and a step coefficient, wherein either of said first and second products is negative, said real operation means for obtaining a real part of an adaptation coefficient from said first and second products; and imaginary operation means for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said step coefficient, and for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said step coefficient, said imaginary operation means for obtaining an imaginary part of an adaptation coefficient from said third and fourth products.
Claim 8
Dependent Claim
181 words
An arithmetic circuit, comprising: real operation means for computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and for computing a second product between an imaginary part signal of said data sequence and a product of an imaginary part signal of said error sequence and a step coefficient, wherein either of said first and second products is negative, said real operation means for obtaining a real part of an adaptation coefficient from said first and second products; and imaginary operation means for computing a third product between said imaginary part signal of said data sequence and a product of said real part signal of said error sequence and said step coefficient, and for computing a fourth product between said real part signal of said data sequence and a product of said imaginary part signal of said error sequence and said step coefficient, said imaginary operation means for obtaining an imaginary part of an adaptation coefficient from said third and fourth products.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-11-19 | 2000-05-20 | 2000-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-19 | 2004-05-20 | 2004-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-19 | 2008-05-20 | 2008-11-19 | $7700.00 | Window Closed / Lapsed |