Automated development of timing diagrams for electrical circuits

Claim 1

A computer-implemented apparatus for constructing timing diagrams to model electrical circuits, comprising: a computer having a monitor attached thereto; data entry means for accepting one or more parameters defining a timing diagram into the computer; means for displaying the timing diagram on the monitor of the computer in response to the parameter accepted into the data entry means, wherein the timing diagram comprises at least one waveform and the waveform comprises one or more edges; wherein one of the parameters comprises a delay that defines a cause and effect relationship between first and second edges and a time between the first and second edges, the time comprises minimum and maximum delay values, and the minimum and maximum delay values define an uncertainty region representing a range of possible time values for an occurrence of the second edge; means for propagating and accumulating uncertainty regions through a plurality of edges connected by delays; means for calculating an uncertainty region for an edge that is a target of one or more delays; wherein one of the parameters comprises a constraint that defines an allowable time between the edges in the waveform, and the constraint comprises minimum an maximum allowable time values, and another one of the parameters comprises a skew between two of the waveforms; means for calculating a timing margin by determining a difference between the minimum and maximum allowable time values between two edges as defined by the constraint and the minimum and maximum delay values between the two edges as calculated by the means for propagating and accumulating uncertainty regions as defined by the delays; and means for adjusting the calculated timing margin based on the skew.