Patent US5576633A successfully refreshed from Google Patents.
US5576633A
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US
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Block specific spare circuit
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1996-11-19
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Expires: 2015-06-07
Abstract
Abstract A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address signals and the internal address. A global spare circuit (28) produces a global spare select signal (GSS), in response to the address match signal. A block spare circuit (34) produces a block spare select signal (BSS), in response to the global spare select signal and the block select signal.
Inventors
- 👤 Robert N. Rountree
- 👤 Dan Cline
- 👤 Darryl G. Walker
- 👤 Francis Hii
- 👤 David W. Bergman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:32
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/80; G11C29/808
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
111 words
A circuit for selecting a block spare in a semiconductor device, the circuit comprising: a programmable circuit, responsive to a first group of address signals and a second group of address signals and first and second stored internal addresses, for producing an address match signal and a block select signal; a global spare circuit, responsive to the address match signal, for producing a global spare select signal; and a plurality of N block spare circuits receiving the global spare select signal, at least one block spare circuit, responsive to the global spare select signal and the block select signal, for producing a block spare select signal, thereby selecting a block spare.
Claim 2
Dependent Claim
111 words
A circuit for selecting a block spare in a semiconductor device, the circuit comprising: a programmable circuit, responsive to a first group of address signals and a second group of address signals and first and second stored internal addresses, for producing an address match signal and a block select signal; a global spare circuit, responsive to the address match signal, for producing a global spare select signal; and a plurality of N block spare circuits receiving the global spare select signal, at least one block spare circuit, responsive to the global spare select signal and the block select signal, for producing a block spare select signal, thereby selecting a block spare.
Claim 3
Dependent Claim
77 words
A circuit, as in claim 1, wherein the programmable circuit further comprises: an address match circuit, arranged for storing the first internal address and responsive to the first group of address signals and to the first internal address, for producing the address match signal; and a block select circuit, arranged for storing the second internal address and responsive to the second group of address signals and to the second internal address, for producing the block select signal.
Claim 4
Dependent Claim
80 words
A circuit, as in claim 1, wherein the programmable circuit further comprise: an address match circuit, arranged for storing the first internal address, responsive to the first group of address signals and the first internal address, for producing the address match signal and an enable signal; and a block select circuit, arranged for storing the second internal address, responsive to the second group of address signals, the second internal address, and the enable signal, for producing the block select signal.
Claim 5
Dependent Claim
25 words
A circuit, as in claim 1, wherein the programmable circuit produces a single block select signal, for enabling the at least one block spare circuit.
Claim 6
Dependent Claim
26 words
A circuit, as in claim 1, wherein the programmable circuit produces log 2 (N) block select signals, for enabling the at least one block spare circuit.
Claim 7
Dependent Claim
34 words
A circuit, as in claim 1, wherein the programmable circuit is coupled to receive the first group of address signals comprising at least one row address signal and at least one column address signal.
Claim 8
Dependent Claim
20 words
A circuit, as in claim 1, wherein the first and second stored internal addresses are stored in nonvolathe memory elements.
Claim 9
Dependent Claim
34 words
A circuit in claim 1, further comprising a block element circuit, responsive to the block select signal and a third address signal, for producing a block element select signal, thereby selecting a block element.
Claim 10
Dependent Claim
57 words
A circuit, as in claim 8, wherein the at least one block spare circuit is responsive to a first logic state of the block select signal, for producing the block spare select signal, and the block element circuit is responsive to a second logic state of the block select signal, for producing the block element select signal.
Claim 11
Dependent Claim
25 words
A circuit, as in claim 8, wherein the programmable circuit produces a single block select signal, for enabling the at least one block spare circuit.
Claim 12
Dependent Claim
26 words
A circuit, as in claim 8, wherein the programmable circuit produces log 2 (N) block select signals, for enabling the at least one block spare circuit.
Claim 13
Dependent Claim
34 words
A circuit, as in claim 8, wherein the programmable circuit is coupled to receive the first group of address signals comprising at least one row address signal and at least one column address signal.
Claim 14
Dependent Claim
73 words
A circuit, as in claim 8, wherein the programmable circuit further comprises: an address match circuit, arranged for storing the first internal address, responsive to the first group of address signals and the first internal address, for producing the address match signal; and a block select circuit, arranged for storing the second internal address, responsive to the second group of address signals and the second internal address, for producing the block select signal.
Claim 15
Dependent Claim
80 words
A circuit, as in claim 8, wherein the programmable circuit further comprises: an address match circuit, arranged for storing the first internal address, responsive to the first group of address signals and the first internal address, for producing the address match signal and an enable signal; and a block select circuit, arranged for storing the second internal address, responsive to the second group of address signals, the second internal address, and the enable signal, for producing the block select signal.
Claim 16
Dependent Claim
89 words
A circuit, as in claim 2, wherein the block select circuit produces the block select signal at an output terminal when the block select circuit is enabled, the block select signal having a first logic state, responsive to a match between the second internal address and the second group of address signals, and having a second logic state, responsive to a mismatch between the second internal address and the second group of address signals, the output terminal having a high impedance state when the block select circuit is disabled.
Claim 17
Dependent Claim
46 words
A circuit, as in claim 15, wherein the block select circuit is enabled when the first internal address matches the first group of address signals, and the block select circuit is disabled when the first internal address does not match the first group of address signals.
Claim 18
Dependent Claim
38 words
A circuit, as in claim 16, further comprising a circuit for coupling the output terminal of the block select circuit to a supply terminal when the first internal address does not match the first group of address signals.
Claim 19
Dependent Claim
25 words
A circuit as in claim 2, wherein the block spare is a spare column of memory cells for replacing a defective column of memory cells.
Claim 20
Dependent Claim
48 words
A circuit as in claim 18, wherein the first group of address signals identify a column address having the defective column of memory cells and wherein the first group of address signals further identifies a row address of a first portion of the spare column of memory cells.
Claim 21
Dependent Claim
60 words
A circuit as in claim 19, wherein the address match circuit further comprises a programmable element having a first logic state and a second logic state, the first logic state selecting the first portion of the spare column of memory cells and the second logic state selecting the first and a second portion of the spare column of memory cells.
Claim 22
Independent Claim
120 words
A method of selecting a block spare in a semiconductor device, the method comprising the steps of: storing an element address in a first programmable circuit; storing a block address in a second programmable circuit; comparing a first group of address signals and a second group of address signals, respectively, to the element and block addresses; transmitting a selection signal to a plurality of selection circuits if the first group of address signals matches the element address; enabling one of the selection circuits if the second group of address signals matches the block addresses; and selecting a block spare if the first group of address signals and the second group of address signals, respectively, match the element and block addresses.
Claim 23
Independent Claim
120 words
A method of selecting a block spare in a semiconductor device, the method comprising the steps of: storing an element address in a first programmable circuit; storing a block address in a second programmable circuit; comparing a first group of address signals and a second group of address signals, respectively, to the element and block addresses; transmitting a selection signal to a plurality of selection circuits if the first group of address signals matches the element address; enabling one of the selection circuits if the second group of address signals matches the block addresses; and selecting a block spare if the first group of address signals and the second group of address signals, respectively, match the element and block addresses.
Claim 24
Dependent Claim
38 words
A method as in claim 21, further comprising the step of selecting a block element if the first group of address signals and the second group of address signals, respectively, do not match the element and block addresses.
Claim 25
Dependent Claim
190 words
A circuit, comprising: a semiconductor device having at least first and second blocks of memory cells, the first block being selected in a first mode of operation, and the first and second blocks being selected in a second mode of operation, each of the first and second blocks having a block element and a block spare; a programmable circuit, responsive to a first group of address signals and a stored internal address, for producing an address match signal and a block select signal; a global spare circuit, responsive to the address match signal, for producing a global spare select signal; a block spare circuit responsive to the global spare select signal and the block select signal, for producing a block spare select signal during the address match signal, thereby selecting the block spare of the first block during the first and second modes of operation; and a block element circuit, responsive to a second group of address signals and the block select signal, for producing a block element select signal during the address match signal, thereby selecting the block element of the second block during the second mode of operation.
Claim 26
Dependent Claim
190 words
A circuit, comprising: a semiconductor device having at least first and second blocks of memory cells, the first block being selected in a first mode of operation, and the first and second blocks being selected in a second mode of operation, each of the first and second blocks having a block element and a block spare; a programmable circuit, responsive to a first group of address signals and a stored internal address, for producing an address match signal and a block select signal; a global spare circuit, responsive to the address match signal, for producing a global spare select signal; a block spare circuit responsive to the global spare select signal and the block select signal, for producing a block spare select signal during the address match signal, thereby selecting the block spare of the first block during the first and second modes of operation; and a block element circuit, responsive to a second group of address signals and the block select signal, for producing a block element select signal during the address match signal, thereby selecting the block element of the second block during the second mode of operation.
Claim 27
Dependent Claim
20 words
A circuit, as in claim 23, wherein the first group of address signals comprises the second group of address signals.
Claim 28
Dependent Claim
29 words
A circuit, as in claim 24, wherein the second group of address signals comprises column address signals, and the first group of address signals further comprises row address signals.
Claim 29
Dependent Claim
30 words
A circuit, as in claim 25, wherein the first mode of operation is a normal mode of operation and the second mode of operation is a test mode of operation.
Claim 30
Dependent Claim
16 words
A circuit, as in claim 23, wherein the semiconductor device comprises K blocks of memory cells.
Claim 31
Dependent Claim
43 words
A circuit, as in claim 27, further comprising a plurality of J programmable circuits, each programmable circuit being responsive to the first group of address signals and a separate stored internal address, for producing J address match signals and K block select signals.
Claim 32
Dependent Claim
29 words
A circuit, as in claim 28, wherein the global spare circuit is coupled to the J address match signals, for producing a plurality of M global spare select signals.
Claim 33
Dependent Claim
41 words
A circuit, as in claim 29, further comprising K block spare circuits, responsive to at least one of the M global spare select signals and at least one of the K block select signals, for producing the block spare select signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-19 | 2000-05-20 | 2000-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-19 | 2004-05-20 | 2004-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-19 | 2008-05-20 | 2008-11-19 | $7700.00 | Window Closed / Lapsed |