Method and apparatus for improving instruction tracing operations in a computer system

Claim 2

A data processing system having an improved execution trace function, the data processing system comprising a bus coupled to a processor, the processor including an instruction cache; at least one instruction pipeline that provides a path for instructions to be fetched from the instruction cache, decoded, and executed; and a control unit that includes circuitry which interprets the decoded instructions and controls the pipeline, wherein the improvement comprises: a register that stores data indicating a special bus cycle to be run on the bus, the special bus cycle including a first message which provides a target linear address of a branch, and optionally, a second message which provides a linear address of an instruction that caused the branch; the register having a first bit that enables/disables the special bus cycle, and a second bit that controls whether the special bus cycle includes only the first message, or both the first and second messages.

Claim 3

The improvement of claim 1 wherein the first message precedes the second message.

Claim 4

The improvement of claim 1 wherein the bus comprises address and data lines, with both the target linear address and the linear address of the instruction which caused the branch being provided on both the address and data lines.

Claim 5

The improvement of claim 3 wherein a lower-order portion and a higher-order portion of bits of the target linear address are respectively provided on the data and address lines during the first message.

Claim 6

In a data processing system that includes a processor coupled to a bus, the processor including an instruction cache; at least one instruction pipeline that provides a path for instructions to be fetched from the instruction cache, decoded, and executed; and a control unit which includes circuitry that interprets the decoded instructions and controls the pipeline, a method of execution tracing comprising the steps of: (a) storing data in a register of the processor which indicates that a special bus cycle is to be run on the bus; (b) setting a first bit in the register to enable the special bus cycle; (c) setting a second bit in the register to control whether the special bus cycle only includes a first message, or includes both the first and a second message, wherein the first message provides a target linear address of a branch, and the second message provides a linear address of an instruction that caused the branch; (d) running the special cycle on the bus.

Claim 7

In a data processing system that includes a processor coupled to a bus, the processor including an instruction cache; at least one instruction pipeline that provides a path for instructions to be fetched from the instruction cache, decoded, and executed; and a control unit which includes circuitry that interprets the decoded instructions and controls the pipeline, a method of execution tracing comprising the steps of: (a) storing data in a register of the processor which indicates that a special bus cycle is to be run on the bus; (b) setting a first bit in the register to enable the special bus cycle; (c) setting a second bit in the register to control whether the special bus cycle only includes a first message, or includes both the first and a second message, wherein the first message provides a target linear address of a branch, and the second message provides a linear address of an instruction that caused the branch; (d) running the special cycle on the bus.

Claim 8

The method according to claim 5 wherein the bus comprises address and data lines, wherein a lower-order portion and a higher-order portion of bits of the target linear address are respectively provided on the address and data lines during the first message.