PC card

Claim 2

A PC card, comprising: a housing having side surfaces and a connector surface communicating with said side surfaces; first contact holes formed on said connector surface and mated with contact pins of a multipin connector and contact pins of a standard pin connector; and second contact holes formed on said connector surface and mated with said contact pins of said multipin connector.

Claim 3

The PC card according to claim 1, wherein said first contact holes are lined up in two rows on said connector surface, and said second contact holes are lined up in a row between said upper and lower rows of said first contact holes lined up in two rows.

Claim 4

The PC card according to claim 2, further comprising incorrect insertion prevention ditches formed on said side surfaces of said housing.

Claim 5

The PC card according to claim 3, further comprising a first incorrect insertion prevention ditch formed on one side surface of said housing, a second incorrect insertion prevention ditch formed on the other side surface of said housing, wherein said first and second incorrect insertion prevention ditches are shaped mutually asymmetrically.

Claim 6

The PC card according to claim 4, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting data through said first contact holes; a semiconductor memory device including a plurality of chips for storing the data; an address input buffer for inputting a first address through said first contact holes and outputting the first address to said semiconductor memory device; a multipin mode address input buffer for inputting a second address through said second contact holes in a multipin mode; and an address decoder for selecting any of said chips comprising said semiconductor memory device according to high-order bits of the first address in a standard pin mode, and selecting any of said chips comprising said semiconductor memory device according to said high-order bits of the first address as well as the second address in the multipin mode.

Claim 7

The PC card according to claim 4, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting first data through said first contact holes in a standard pin mode, and inputting or outputting second data through said first and second contact holes in a multipin mode; a semiconductor memory device including a plurality of chips for storing the first data in the standard pin mode, and storing the second data in the multipin mode; an address input buffer for inputting an address through said first contact holes and outputting said address to said semiconductor memory device; and an address decoder for selecting any of said chips comprising said semiconductor memory device according to high-order bits of said address.

Claim 8

The PC card according to claim 4, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting first data through said first contact holes in a standard pin mode and for inputting or outputting second data through said first and second contact holes in a multipin mode; a semiconductor memory device including a plurality of chips, storing the first data in the standard pin mode, and storing the second data in the multipin mode; an address input buffer for inputting a first address through said first contact holes and outputting the first address to said semiconductor memory device; a multipin mode address input buffer for inputting the second address through said second contact holes in the multipin mode; and an address decoder for selecting any of said chips comprising said semiconductor memory device according to high-order bits of the first address in the standard pin mode, and selecting any of said chips comprising said semiconductor memory device according to said high-order bits of the first address as well as the second address in the multipin mode.

Claim 9

The PC card according to claim 4, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting first data through said first contact holes in a standard pin mode, and inputting or outputting second data through said first and second contact holes in a multipin mode; a semiconductor memory device including a plurality of chips for storing the first data in the standard pin mode, and for storing the second data in the multipin mode; an offset circuit, which in the standard pin mode, inputs an first address through said first contact holes, outputs the first address to said semiconductor memory device, and adds the retained offset address to the first address, and which in the multipin mode, inputs the first address through said first contact holes, outputs the first address to said semiconductor memory device, and inputs a second address through said second contact holes; and an address decoder for selecting any of said chips constituting said semiconductor memory device according to high-order bits of an address resulting from the addition in the standard pin mode, and selecting any of said chips comprising said semiconductor memory device according to said high-order bits of the first address as well as the second address in the multipin mode.

Claim 10

The PC card according to claim 4, wherein said first and second incorrect insertion prevention ditches are larger than incorrect insertion prevention ditches of a PC card that can be coupled with said standard pin connector alone.

Claim 11

The PC card according to claim 9, wherein the sectional areas of said first and second incorrect insertion prevention ditches are larger than those of incorrect insertion prevention ditches of a PC card that can be coupled with said standard pin connector alone.

Claim 12

The PC card according to claim 9, wherein the sectional areas of said first and second incorrect insertion prevention ditches are larger in the direction of thickness of said card than those of incorrect insertion prevention ditches of a PC card that can be coupled with said standard pin connector alone.

Claim 13

The PC card according to claim 11, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting first data through said first contact holes in a standard pin mode, and inputting or outputting second data through said first and second contact holes in a multipin mode; a semiconductor memory device including a plurality of chips for storing the first data in the standard pin mode, and storing the second data in the multipin mode; an address input buffer for inputting a first address through said first contact holes and outputting the first address to said semiconductor memory device; a multipin mode address buffer for inputting a second address through said second contact holes in the multipin mode; and an address decoder for selecting any of said chips comprising said semiconductor memory device according to high-order bits of the first address in the standard pin mode, and selecting any of said chips comprising said semiconductor memory device according to said high-order bits of the first address as well as the second address.

Claim 14

The PC card according to claim 10, wherein the sectional areas of said first and second incorrect insertion prevention ditches are larger in the direction of the width of said PC card than those of incorrect insertion prevention ditches of a PC card that can be coupled with said standard pin connector alone.

Claim 15

The PC card according to claim 13, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting first data through said first contact holes in a standard pin mode, and inputting or outputting second data through said first and second contact holes in a multipin mode; a semiconductor memory device including a plurality of chips, storing the second data in the multipin mode; an address input buffer for inputting a first address through said first contact holes and outputting the first address to said semiconductor memory device; a multipin mode address buffer for inputting a second address through said second contact holes in the multipin mode; and an address decoder for selecting any of said chips comprising said semiconductor memory device according to high-order bits of the first address in the standard pin mode, and selecting any of said chips comprising said semiconductor memory device according to said high-order bits of the first address as well as the second address.

Claim 16

The PC card according to claim 9, wherein the depths in the longitudinal direction of said card of said first and second incorrect insertion prevention ditches are larger than those of incorrect insertion prevention ditches of a PC card that can be coupled with said standard pin connector alone.

Claim 17

The PC card according to claim 15, further comprising: a mode control circuit for controlling read and write modes; a data input/output buffer for inputting or outputting first data through said first contact holes in a standard pin mode and for inputting or outputting second data thorough said first and second contact holes in a standard pin mode and for inputting or outputting second data through said first and second contact holes in a multipin mode; a semiconductor memory device including a plurality of chips for storing the first data in the standard pin mode, and storing the second data in the multipin mode; an address input buffer for inputting a first address through said first contact holes and outputting the first address to said semiconductor memory device; a multipin mode address buffer for inputting a second address through said second contact holes in the multipin mode; and an address decoder for selecting any of said chips comprising said semiconductor memory device according to high-order bits of the first address in the standard pin mode, and selecting any of said chips comprising said semiconductor memory device according to said high-order bits of the first address as well as the second address.