US5572708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware simulator capable of dealing with a description of a functional level
Assignee: NEC Corp
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Filing: 1993-06-10
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Granted: 1996-11-05
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Expires: 2013-06-10
Abstract
Abstract In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences. Preferably, a flag memory is used to memorize, in correspondence to the respective sentences, flags indicative of whether or not the initial values are changed while simulation is in progress. One of the sentences is selected as the current sentence only when the flag indicates a change for the sentence in question. More preferably, the sentence calculating unit is accompanied by the input and output first-in first-out memories for enabling calculation of a plurality of successive ones of the sentences.
Inventors
- 👤 Shigeru Takasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:55
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
244 words
A logic simulator comprising: a descriptor memory for memorizing descriptors descriptive of a logic circuit as memorized descriptors, each descriptor of said memorized descriptors being one of variables and functional operators; a first register connected to said descriptor memory for memorizing each variable of said memorized descriptors as a first datum; a second register for memorizing a second datum, said second register being coupled to said first register via a signal path for selectively supplying said second datum from said second register to said first register; calculating means connected to said first and said second registers and said descriptor memory for carrying out calculation on said first and said second data on the basis of one of said functional operators of said memorized operators to provide a result of calculation, said one of the functional operators joining said first and said second data; refreshing means connected to said second register and said calculating means for carrying out refreshment of said second datum by said result of calculation; and control means connected to said descriptor memory, said first and said second registers, said calculating means, and said refreshing means for controlling transfer of said each variable and said one of the functional operators from said descriptor memory to said first register, said calculating means, and said refreshing means, said control means controlling the transfer of said variables and functional operators to said first and second registers, and said calculating means sequentially in a serial fashion.
Claim 2
Dependent Claim
244 words
A logic simulator comprising: a descriptor memory for memorizing descriptors descriptive of a logic circuit as memorized descriptors, each descriptor of said memorized descriptors being one of variables and functional operators; a first register connected to said descriptor memory for memorizing each variable of said memorized descriptors as a first datum; a second register for memorizing a second datum, said second register being coupled to said first register via a signal path for selectively supplying said second datum from said second register to said first register; calculating means connected to said first and said second registers and said descriptor memory for carrying out calculation on said first and said second data on the basis of one of said functional operators of said memorized operators to provide a result of calculation, said one of the functional operators joining said first and said second data; refreshing means connected to said second register and said calculating means for carrying out refreshment of said second datum by said result of calculation; and control means connected to said descriptor memory, said first and said second registers, said calculating means, and said refreshing means for controlling transfer of said each variable and said one of the functional operators from said descriptor memory to said first register, said calculating means, and said refreshing means, said control means controlling the transfer of said variables and functional operators to said first and second registers, and said calculating means sequentially in a serial fashion.
Claim 3
Dependent Claim
205 words
A logic simulator as claimed in claim 1, wherein: said descriptor memory memorizes a first, a second, and a third variable and a first and a second functional operator as said memorized descriptors, said first functional operator joining said first and said second variables; said control means controlling said transfer, said calculation, and said refreshment in response to an output of said descriptor memory, and including means for causing said first and said second registers to memorize a first set of data including said first and said second variables as said first and said second data before refreshment of said refreshing means and for causing said first and said second registers to memorize, after refreshment of said refreshing means, as said first and said second data a second set of data including said third variable and a first result of calculation of said calculating means which carries out calculation on said first and said second variables on the basis of said first functional operator, said third variable and said first result being used as said first and said second data in said calculating means to be produced as a second result of calculation of said calculating means on the basis of said second functional operator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |