Interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging break point in an instruction code

Claim 2

An information processing device for permitting generation of an interrupt signal requested by a break signal initiated by a breakpoint set in an instruction code, comprising: means for outputting an execution completion signal indicating completion of execution of said instruction code; and means for generating an interrupt signal using said break signal and said execution completion signal when said breakpoint is set in or after a second byte of said instruction code.

Claim 3

The information processing device of claim 1, wherein said means for generating an interrupt signal comprises: memory means for storing said break signal; and means for latching said break signal from said memory means and for outputting said interrupt signal at the occurrence of said execution completion signal.

Claim 4

The information processing device of claim 1, comprising: means for outputting an execution start signal indicating a start of execution of said instruction code, wherein said means for generating an interrupt signal outputs said interrupt signal using said break signal and said execution start signal when having received said break signal that is output at the time of detection of a breakpoint set in a first byte of said instruction code.

Claim 5

The information processing device of claim 3, wherein said means for outputting an interrupt signal comprises: a first flip-flop for receiving said break signal as a data and for outputting said interrupt signal after receiving said execution start signal; a second flip-flop for receiving and storing said break signal as a data; and a third flip-flop for receiving an output signal from said second flip-flop and outputting said interrupt signal after receiving said execution completion signal.

Claim 6

The information processing device of claim 4, further comprising an OR-circuit for generating a new interrupt signal after receiving either an interrupt signal output from said first flip-flop or an interrupt signal output from said third flip-flop.

Claim 7

The information processing device of claim 4, comprising: a selection circuit for selecting output timing of said interrupt signal from either a time before or after execution of said instruction code; and a register for outputting a switching instruction to said selection circuit, wherein said selection circuit outputs one of an interrupt signal output from said first flip-flop when the output timing of said interrupt signal is set in before-execution of said instruction code, and outputs an interrupt signal output from said third flip-flop when the output timing of said interrupt signal is set in after-execution of said instruction code.

Claim 8

The information processing device of claim 4, further comprising an interrupt processing section for executing an interrupt processing and for outputting a reset signal for resetting said second flip-flop, after receiving said interrupt signal.

Claim 9

The information processing device of claim 1, wherein said break signal is output from a breakpoint detection circuit provided outside of said information processing device, and said breakpoint detection circuit outputs said break signal after detecting an address where a breakpoint for stopping execution of said instruction code is set.

Claim 10

The information processing device of claim 1, wherein said break signal is output from a breakpoint detection circuit provided within said information processing device and said breakpoint detection circuit outputs said break signal after detecting said address where a breakpoint for stopping execution of said instruction code is set.

Claim 11

An information processing device for generating an interrupt signal when having received a request for an interrupt by a break signal corresponding to a fetched instruction code, comprising: means for outputting an execution start signal indicating a start of execution of said instruction code; means for outputting an execution completion signal indicating a completion of execution of said instruction code; a first flip-flop for receiving said break signal as a data and for outputting said interrupt signal after receiving said execution start signal; a second flip-flop for receiving and storing said break signal as dam; and a third flip-flop for receiving said data stored in said second flip-flop and for outputting said interrupt signal after receiving said execution completion signal.

Claim 12

An information processing device for generating an interrupt signal when having received a request for an interrupt by a break signal corresponding to a fetched instruction code, comprising: means for outputting an execution start signal indicating a start of execution of said instruction code; means for outputting an execution completion signal indicating a completion of execution of said instruction code; a first flip-flop for receiving said break signal as a data and for outputting said interrupt signal after receiving said execution start signal; a second flip-flop for receiving and storing said break signal as dam; and a third flip-flop for receiving said data stored in said second flip-flop and for outputting said interrupt signal after receiving said execution completion signal.

Claim 13

The information processing device of claim 10, further comprising an OR-circuit for generating a new interrupt signal after receiving either an interrupt signal output from said first flip-flop or an interrupt signal output from said third flip-flop.

Claim 14

The information processing device of claim 10, further comprising: a selection circuit for selecting output timing of said interrupt signal from either before or after execution of said instruction code; and a register for outputting a switching instruction to said selection circuit, wherein said selection circuit outputs an interrupt signal from one of said first flip-flop when the output timing of said interrupt signal is set in before-execution of said instruction code, and said third flip-flop when the output timing of said interrupt signal is set in after-execution of said instruction code.

Claim 17

The method of claim 13, further comprising the steps of: outputting an execution start signal for indicating a start of execution of said instruction code; and generating said interrupt signal with said break signal and said execution start signal when said breakpoint is set in a first byte of said instruction code.

Claim 18

An interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging breakpoint placed in an instruction code, comprising: means for generating an instruction code execution start signal; means for generating an instruction code execution completion signal; a first latch for receiving a break signal generated from said breakpoint, said first latch outputting a before-execution interrupt signal upon generation of said instruction code execution start signal; a second latch for receiving said break signal generated from said breakpoint and holding a stored break signal upon generation of said instruction code execution completion signal; a third latch for receiving said stored break signal and for outputting an after-execution interrupt signal; and interrupt selection means connected to outputs of said first and third latches, said interrupt selection means selecting said before-execution interrupt signal if said breakpoint is positioned in a first byte of said instruction code, and selecting said after-execution interrupt signal if said breakpoint is positioned in or after a second byte of said instruction code.

Claim 19

An interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging breakpoint placed in an instruction code, comprising: means for generating an instruction code execution start signal; means for generating an instruction code execution completion signal; a first latch for receiving a break signal generated from said breakpoint, said first latch outputting a before-execution interrupt signal upon generation of said instruction code execution start signal; a second latch for receiving said break signal generated from said breakpoint and holding a stored break signal upon generation of said instruction code execution completion signal; a third latch for receiving said stored break signal and for outputting an after-execution interrupt signal; and interrupt selection means connected to outputs of said first and third latches, said interrupt selection means selecting said before-execution interrupt signal if said breakpoint is positioned in a first byte of said instruction code, and selecting said after-execution interrupt signal if said breakpoint is positioned in or after a second byte of said instruction code.

Claim 20

An interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging breakpoint placed in an instruction code as recited in claim 15, further comprising an OR gate having inputs receiving said before-execution interrupt signal and said after-execution interrupt signal and having an output connecting to said interrupt selection means.

Claim 21

An interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging breakpoint placed in an instruction code as recited in claim 16, further comprising: a selector receiving as inputs said OR gate output and said after-execution interrupt signal and having an output connected to said interrupt selection means; and a register connected to said selector for storing data controlling the output of said selector.

Claim 22

An interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging breakpoint placed in an instruction code as recited in claim 15 wherein said first latch comprises a D flip-flop, said second latch comprises an SR flip-flop, and said third latch comprises a D flip-flip.

Claim 23

An interrupt processing device for controlling the timing of an interrupt signal initiated by a debugging breakpoint placed in an instruction code as recited in claim 18 wherein said interrupt selection means outputs a reset signal for resetting said SR flip-flop.