US5493659A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor providing fast break in program execution
Assignee: Hitachi Ltd
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Filing: 1990-12-13
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Granted: 1996-02-20
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Expires: 2010-12-13
Abstract
Abstract A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.
Inventors
- 👤 Keiichi Kurakazu
- 👤 Yoshikazu Aoto
- 👤 Shiro Baba
- 👤 Satoshi Masuda
- 👤 Hiroyuki Kida
- 👤 Shinji Kawashima
- 👤 Yoshiaki Naruse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
137 words
An integrated data processor comprising an instruction register for holding an instruction to be executed; fetch means for applying instructions in sequence to said instruction register; decoding means for decoding an instruction held in said instruction register and for producing control signals based on the decoded instruction; bus means for supplying data and instructions; and execution means responsive to said control signals produced by said decoding means for performing an arithmetic operation on data received on said bus means; wherein said fetch means includes memory circuit means for storing only an interrupt instruction and switching means connected to said memory circuit means and said bus means and responsive to an external control signal for selectively applying either an instruction received on said bus means or said interrupt instruction from said memory circuit means to said instruction register.
Claim 2
Dependent Claim
137 words
An integrated data processor comprising an instruction register for holding an instruction to be executed; fetch means for applying instructions in sequence to said instruction register; decoding means for decoding an instruction held in said instruction register and for producing control signals based on the decoded instruction; bus means for supplying data and instructions; and execution means responsive to said control signals produced by said decoding means for performing an arithmetic operation on data received on said bus means; wherein said fetch means includes memory circuit means for storing only an interrupt instruction and switching means connected to said memory circuit means and said bus means and responsive to an external control signal for selectively applying either an instruction received on said bus means or said interrupt instruction from said memory circuit means to said instruction register.
Claim 3
Dependent Claim
33 words
An integrated data processor according to claim 1, wherein said fetch means further includes storage means connected between said switching means and said instruction register for buffering instructions received from said switching means.
Claim 4
Dependent Claim
40 words
An integrated data processor according to claim 1, wherein said fetch means further includes storage means connected between said switching means and said instruction register for effecting an instruction holding function for a program of instructions for a data process.
Claim 5
Dependent Claim
29 words
An integrated data processor according to claim 1, wherein said execution means includes first means responsive to execution of said interrupt instruction for inhibiting acceptance of further interrupt requests.
Claim 6
Dependent Claim
37 words
An integrated data processor according to claim 4, wherein said execution means includes second means responsive to execution of said interrupt instruction for generating a status signal to be outputted externally which indicates an interrupt acceptance status.
Claim 7
Dependent Claim
35 words
An integrated data processor according to claim 5, wherein said second means is responsive to execution of a predetermined instruction in said execution means for changing said status signal to release said interrupt acceptance status.
Claim 8
Dependent Claim
29 words
An integrated data processor according to claim 5, wherein said second means is responsive to a control signal for changing said status signal to release said interrupt acceptance status.
Claim 9
Dependent Claim
56 words
An integrated data processor according to claim 1, further comprising mode setting means for providing a mode setting signal, said fetch means being responsive to receipt of both said external control signal and said mode setting signal for operating said switching means to supply said interrupt instruction from said memory circuit means to said instruction register.
Claim 10
Dependent Claim
21 words
An integrated data processor according to claim 1, wherein said data processor is a microcomputer unit formed on a single chip.
Claim 11
Dependent Claim
224 words
A data processing system comprising: a target processor on a single chip for performing operations in response to execution of programs of instructions forming a user space; and a main processor coupled to said target processor for performing operations as an in-circuit emulator, including input means for inputting a break command and a break address, and break circuit means responsive to said break address and an address signal received from said target processor for generating a break signal; wherein said target processor includes an instruction register for holding an instruction to be executed; fetch means for applying instructions in sequence to said instruction register; decoding means for decoding an instruction held in said instruction register and for producing control signals based on the decoded instruction; bus means for supplying data and instructions; and execution means responsive to said control signals produced by said decoding means for performing an arithmetic operation on data received on said bus means; wherein said fetch means includes memory circuit means for storing only an interrupt instruction and switching means connected to said memory circuit means and said bus means and responsive to the absence or presence of said break signal from said break circuit means for selectively applying either an instruction received on said bus means or said interrupt instruction from said memory circuit means to said instruction register.
Claim 12
Dependent Claim
224 words
A data processing system comprising: a target processor on a single chip for performing operations in response to execution of programs of instructions forming a user space; and a main processor coupled to said target processor for performing operations as an in-circuit emulator, including input means for inputting a break command and a break address, and break circuit means responsive to said break address and an address signal received from said target processor for generating a break signal; wherein said target processor includes an instruction register for holding an instruction to be executed; fetch means for applying instructions in sequence to said instruction register; decoding means for decoding an instruction held in said instruction register and for producing control signals based on the decoded instruction; bus means for supplying data and instructions; and execution means responsive to said control signals produced by said decoding means for performing an arithmetic operation on data received on said bus means; wherein said fetch means includes memory circuit means for storing only an interrupt instruction and switching means connected to said memory circuit means and said bus means and responsive to the absence or presence of said break signal from said break circuit means for selectively applying either an instruction received on said bus means or said interrupt instruction from said memory circuit means to said instruction register.
Claim 13
Dependent Claim
36 words
A data processing system according to claim 9, wherein said execution means in said target processor includes means responsive to execution of said interrupt instruction for generating a status signal which indicates an interrupt acceptance status.
Claim 14
Dependent Claim
37 words
A data processing system according to claim 11, further including means responsive to said status signal for switching operations in the data processing system from said target processor to said main processor to effect in-circuit emulator operations.
Claim 15
Dependent Claim
37 words
A data processing system according to claim 12, wherein said status signal generating means in said target processor is responsive to execution of a predetermined instruction for changing said status signal to release said interrupt acceptance status.
Claim 16
Dependent Claim
35 words
A data processing system according to claim 12, wherein said status signal generating means in said target processor is responsive to a control signal for changing said status signal to release said interrupt acceptance status.
Claim 17
Dependent Claim
150 words
An integrated microprocessor having first and second operating modes comprising: a processor for executing a first predetermined data processing according to a program to be developed in the first operating mode, and executing a second predetermined data processing according to an emulator program in the second operating mode; a control signal input terminal for receiving an externally generated break signal having a first state and a second state, and means for changing the operation of the processor to the second operating mode from the first operating mode in response to said externally generated break signal changing from the first state to the second state; and an output terminal for providing an internally generated break acknowledge signal which has a first level when the processor is in the first operating mode, and a second level when the processor is in the second operating mode, and which is provided from the processor.
Claim 18
Dependent Claim
150 words
An integrated microprocessor having first and second operating modes comprising: a processor for executing a first predetermined data processing according to a program to be developed in the first operating mode, and executing a second predetermined data processing according to an emulator program in the second operating mode; a control signal input terminal for receiving an externally generated break signal having a first state and a second state, and means for changing the operation of the processor to the second operating mode from the first operating mode in response to said externally generated break signal changing from the first state to the second state; and an output terminal for providing an internally generated break acknowledge signal which has a first level when the processor is in the first operating mode, and a second level when the processor is in the second operating mode, and which is provided from the processor.
Claim 19
Dependent Claim
33 words
An integrated microprocessor according to claim 15, wherein the break acknowledge signal is changed to the first level from the second level when the processor executes a return instruction in the emulator program.
Claim 20
Dependent Claim
200 words
An integrated microprocessor, comprising: first input terminals for receiving mode control signals; mode determining means coupled to receive the mode control signals for providing a mode signal in accordance with the mode control signals, wherein the mode determining means provides an emulator mode signal when the mode control signals indicate that the integrated microprocessor is to be operated in the emulator mode; a processor for executing a first predetermined data processing according to a program to be developed in a first operating mode, and executing a second predetermined data processing according to an emulator program in a second operating mode when the mode determining means provides the emulator mode signal; means, including a second input terminal for receiving a break signal having a first state and a second state, for changing operation of the processor to the second operating mode from the first operating mode in response to receipt of a break signal changing from the first state to the second state; and a gate circuit coupled to the second input terminal and to the mode determining means and for validating the break signal on the second input terminal only when the mode determining means generates the emulator mode signal.
Claim 21
Dependent Claim
200 words
An integrated microprocessor, comprising: first input terminals for receiving mode control signals; mode determining means coupled to receive the mode control signals for providing a mode signal in accordance with the mode control signals, wherein the mode determining means provides an emulator mode signal when the mode control signals indicate that the integrated microprocessor is to be operated in the emulator mode; a processor for executing a first predetermined data processing according to a program to be developed in a first operating mode, and executing a second predetermined data processing according to an emulator program in a second operating mode when the mode determining means provides the emulator mode signal; means, including a second input terminal for receiving a break signal having a first state and a second state, for changing operation of the processor to the second operating mode from the first operating mode in response to receipt of a break signal changing from the first state to the second state; and a gate circuit coupled to the second input terminal and to the mode determining means and for validating the break signal on the second input terminal only when the mode determining means generates the emulator mode signal.
Claim 22
Dependent Claim
42 words
An integrated microprocessor according to claim 17, further comprising: third input terminals for receiving interrupt request signals; and interrupt control means coupled to the third input terminals and to the gate circuit and for delivering an interrupt control signal to the processor.
Claim 23
Dependent Claim
102 words
An integrated microprocessor according to claim 18, further comprising: check means coupled to the mode determining means for producing an output as to whether or not the integrated microprocessor is in the emulator mode to the processor when the check means receives a check request signal from the processor; wherein the operation of the processor is changed to the second operating mode from the first operating mode in response to a break signal changed from the first state to the second state after the processor receives the output indicating that the integrated microprocessor is in the emulator mode from the check means.
Claim 24
Dependent Claim
52 words
An integrated microprocessor according to claim 17, further comprising: an output terminal for outputting a break acknowledge signal which has a first level when the processor is in the first operating mode, and a second level when the processor is in the second operating mode, and which is provided from the processor.
Claim 25
Dependent Claim
33 words
An integrated microprocessor according to claim 20, wherein the break acknowledge signal is changed to the first level from the second level when the processor executes a return instruction in the emulator program.
Claim 26
Dependent Claim
240 words
An integrated microprocessor, comprising: first input terminals for receiving mode control signals; mode determining means coupled to receive the mode control signals for providing a mode signal in accordance with the mode control signals, wherein the mode determining means provides an emulator mode signal when the mode control signals indicate that the integrated microprocessor is to be operated in the emulator mode; a processor for executing a first predetermined data processing according to a program to be developed in a first operating mode, and executing a second predetermined data processing according to an emulator program in a second operating mode when the integrated microprocessor is in the emulator mode, wherein the program to be developed includes a break instruction for changing the operation mode of the processor from the first operating mode to the second operating mode, wherein the operation mode of the processor is changed to the second operating mode from the first operating mode in response to execution of the break instruction by the processor; and check means coupled to the mode determining means for producing an output as to whether or not the integrated microprocessor is in the emulator mode and for sending said output to the processor when the check means receives a check request signal from the processor; wherein the processor executes the break instruction after the processor receives the output indicating that the integrated microprocessor is in the emulator mode from the check means.
Claim 27
Dependent Claim
240 words
An integrated microprocessor, comprising: first input terminals for receiving mode control signals; mode determining means coupled to receive the mode control signals for providing a mode signal in accordance with the mode control signals, wherein the mode determining means provides an emulator mode signal when the mode control signals indicate that the integrated microprocessor is to be operated in the emulator mode; a processor for executing a first predetermined data processing according to a program to be developed in a first operating mode, and executing a second predetermined data processing according to an emulator program in a second operating mode when the integrated microprocessor is in the emulator mode, wherein the program to be developed includes a break instruction for changing the operation mode of the processor from the first operating mode to the second operating mode, wherein the operation mode of the processor is changed to the second operating mode from the first operating mode in response to execution of the break instruction by the processor; and check means coupled to the mode determining means for producing an output as to whether or not the integrated microprocessor is in the emulator mode and for sending said output to the processor when the check means receives a check request signal from the processor; wherein the processor executes the break instruction after the processor receives the output indicating that the integrated microprocessor is in the emulator mode from the check means.
Claim 28
Dependent Claim
79 words
An integrated microprocessor according to claim 22, further comprising: a second input terminal for receiving a break signal having a first state and a second state, wherein the operation of the processor is changed to the second operating mode from the first operating mode in response to a break signal changed from the first state to the second state after the processor receives the output indicating that the integrated microprocessor is in the emulator mode from the check means.
Claim 29
Dependent Claim
45 words
An integrated microprocessor according to claim 23, further comprising: a gate circuit coupled to the second input terminal and to the mode determining means and for validating the break signal on the second input terminal only when the determining means generates the emulator mode signal.
Claim 30
Dependent Claim
43 words
An integrated microprocessor according to claim 24, further comprising: third input terminals for receiving interrupt request signals; and interrupt control means coupled to the interrupt signal input terminals and to the gate circuit and for delivering an interrupt control signal to the processor.
Claim 31
Dependent Claim
52 words
An integrated microprocessor according to claim 25, further comprising: an output terminal for outputting a break acknowledge signal which has a first level when the processor is in the first operating mode, and a second level when the processor is in the second operating mode, and which is provided from the processor.
Claim 32
Dependent Claim
37 words
An integrated microprocessor according to claim 26, wherein the break acknowledge signal is changed to the first level from the second level in response to execution of a return instruction in the emulator program by the processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |