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US5572471A
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Redundancy scheme for memory circuits
Assignee: SK Hynix America Inc
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Filing: 1995-08-17
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Granted: 1996-11-05
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Expires: 2015-08-17
Abstract
Abstract A redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. The invention does not require disabling a defective element and allows it to operate and generate bad data. The circuit is designed such that the redundant element is able to override the defective element. Various approaches to row and column redundancy based on this principal are disclosed for memory circuit such as dynamic and static random access memories.
Inventors
- 👤 Robert J. Proebsting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C7/00; G11C7/12
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
86 words
A random access memory circuit comprising: a main memory column select transistor for coupling a column line to a data line; a data sense amplifier coupled to the data line; and a redundant column select transistor for coupling a redundant column line to the data line, wherein the redundant column select transistor has a larger channel width to length ratio than the main memory column select transistor, whereby a signal from the redundant column select transistor overrides a signal from the main memory column select transistor.
Claim 2
Dependent Claim
86 words
A random access memory circuit comprising: a main memory column select transistor for coupling a column line to a data line; a data sense amplifier coupled to the data line; and a redundant column select transistor for coupling a redundant column line to the data line, wherein the redundant column select transistor has a larger channel width to length ratio than the main memory column select transistor, whereby a signal from the redundant column select transistor overrides a signal from the main memory column select transistor.
Claim 3
Dependent Claim
71 words
A random access memory circuit comprising: a column sense amplifier having a first and second transistors coupled to a column line; and a redundant column sense amplifier having a third and fourth transistors coupled to a redundant column line, wherein, the third and fourth transistors in the redundant column sense amplifier have a larger channel width to length ratio compared to the first and second transistors in the column sense amplifier.
Claim 4
Dependent Claim
71 words
A random access memory circuit comprising: a column sense amplifier having a first and second transistors coupled to a column line; and a redundant column sense amplifier having a third and fourth transistors coupled to a redundant column line, wherein, the third and fourth transistors in the redundant column sense amplifier have a larger channel width to length ratio compared to the first and second transistors in the column sense amplifier.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |