US5572114A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit with bipolar transistor connected in reverse arrangement
Assignee: Texas Instruments Inc
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Filing: 1994-04-18
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Granted: 1996-11-05
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Expires: 2014-04-18
Abstract
Abstract A semiconductor integrated circuit for performing a current mirror function and capable of operating stably at a low supply voltage to yield an output current nearly equal to the reference current. The current mirror circuit includes a pair of horizontal type pnp transistors and a vertical type npn transistor having an area almost equal to that of either of the pair of horizontal transistors, the vertical type npn transistor being used as a reverse transistor. A current source supplies the base current of the horizontal transistors as well as the collector current of the vertical transistor. Because of its structure, it is possible for the vertical transistor to have a base area and static forward current transfer ratio greater than those of the horizontal transistors. Since the emitter area of the vertical transistor is large, even when it is used to function as a reverse transistor, its static forward current transfer ratio is high. Through using this vertical transistor as a reverse transistor, the effect of the base current of the horizontal transistors on the reference current is reduced.
Inventors
- 👤 Kouzou Ichimaru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:50
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
252 words
A current mirror circuit comprising: a first transistor of one conductivity type having a power supply terminal, an output terminal and a control terminal; a second transistor of the same one conductivity type as said first transistor and having a power supply terminal, an output terminal and a control terminal; the power supply terminals and the control terminals of said first and second transistors being respectively commonly connected to each other; a third transistor of opposite conductivity type to said one conductivity type of said first and second transistors and having a power supply terminal, an output terminal and a control terminal; a first current source having an input and an output, the input of said first current source being connected to the output terminal of said first transistor; and a second current source having an input and an output, the input of said second current source being connected to the output terminal of said third transistor and to a node located in the connection between the control terminals of said first and second transistors; said third transistor being a bipolar transistor having base, collector and emitter electrodes connected in reverse arrangement with the emitter of said third transistor being the power supply terminal and the collector being the output terminal connected to the input of said second current source; and said second current source drawing a bias current through said third transistor and from the control terminals of said first and second transistors to render said first and second transistors conductive.
Claim 2
Dependent Claim
252 words
A current mirror circuit comprising: a first transistor of one conductivity type having a power supply terminal, an output terminal and a control terminal; a second transistor of the same one conductivity type as said first transistor and having a power supply terminal, an output terminal and a control terminal; the power supply terminals and the control terminals of said first and second transistors being respectively commonly connected to each other; a third transistor of opposite conductivity type to said one conductivity type of said first and second transistors and having a power supply terminal, an output terminal and a control terminal; a first current source having an input and an output, the input of said first current source being connected to the output terminal of said first transistor; and a second current source having an input and an output, the input of said second current source being connected to the output terminal of said third transistor and to a node located in the connection between the control terminals of said first and second transistors; said third transistor being a bipolar transistor having base, collector and emitter electrodes connected in reverse arrangement with the emitter of said third transistor being the power supply terminal and the collector being the output terminal connected to the input of said second current source; and said second current source drawing a bias current through said third transistor and from the control terminals of said first and second transistors to render said first and second transistors conductive.
Claim 3
Dependent Claim
44 words
A current mirror circuit as set forth in claim 1, wherein said first and second transistors of the same one conductivity type are respective first and second bipolar transistors having base, collector and emitter electrodes with the bases and emitters being connected in common.
Claim 4
Dependent Claim
27 words
A current mirror circuit as set forth in claim 2, wherein said first and second transistors are PNP transistors, and said third transistor is an NPN transistor.
Claim 5
Dependent Claim
100 words
A current mirror circuit as set forth in claim 3, wherein said first and second transistors are lateral PNP transistors of at least substantially identical structure and area and having at least substantially the same operating characteristics; and said third transistor is a vertical NPN transistor having a total area approximately equal to that of one of said lateral PNP transistors and including a base-collector junction area larger than the respective base-emitter junction areas of said lateral PNP transistors; whereby the base-emitter voltage of said vertical NPN transistor is reducible without adversely affecting the operation of the current mirror circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |