US4937515A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low supply voltage current mirror circuit
Assignee: Toshiba Corp
•
Filing: 1989-08-31
•
Granted: 1990-06-26
•
Expires: 2009-08-31
Abstract
Abstract The current mirror circuit comprises a feedback transistor whose emitter and collector are connected between the collector and base of the input transistor. The base of the feedback transistor is grounded. Due to the presence of the feedback transistor, the potential at the collector of the input transistor can be set at a potential which is lowered from the Vcc potential by a saturation voltage between the emitter and collector of the input transistor.
Inventors
- 👤 Hiroshi Yoshino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:35
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
98 words
A current mirror circuit comprising: a first transistor whose emitter is connected to a first potential; a second transistor whose emitter and collector are inserted between the collector and base of said first transistor and whose base is grounded; an input current source circuit which is grounded between the collector of said first transistor and a second potential; a constant current source connected between the base of said first transistor and the second potential; and a third transistor whose emitter is connected to the first potential and whose base is connected to the base of said first transistor.
Claim 2
Dependent Claim
98 words
A current mirror circuit comprising: a first transistor whose emitter is connected to a first potential; a second transistor whose emitter and collector are inserted between the collector and base of said first transistor and whose base is grounded; an input current source circuit which is grounded between the collector of said first transistor and a second potential; a constant current source connected between the base of said first transistor and the second potential; and a third transistor whose emitter is connected to the first potential and whose base is connected to the base of said first transistor.
Claim 3
Dependent Claim
19 words
A current mirror circuit according to claim 1, in which said first to third transistors are of pnp type.
Claim 4
Dependent Claim
19 words
A current mirror circuit according to claim 1, in which said first to third transistors are of npn type.
Claim 5
Dependent Claim
25 words
A current mirror circuit according to claim 1, in which said first transistor is an input transistor and said third transistor is an output transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |