Patent US5570376A successfully refreshed from Google Patents.
US5570376A
Expired / Lapsed
US
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Method and apparatus for identifying faults within a system
Assignee: Oracle America Inc
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Filing: 1994-10-05
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Granted: 1996-10-29
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Expires: 2014-10-05
Abstract
Abstract Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets. The lists of candidate faulty gates are input to an X-Y location tool which determines the physical location on the integrated circuit of each of the candidate faulty gates to facilitate the efficient examination of each of the candidate faulty gates by test personnel.
Inventors
- 👤 Ramachandra P. Kunda
- 👤 Adam C. Malamy
- 👤 Marc Levitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:30
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2257
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
153 words
A method for identifying elements of a faulty system, that are likely to contain the faults of the system, based on a set of test vectors output from the system wherein each test vector contains a set of test values, the method comprising the steps of: comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; identifying a set of candidate faulty elements for each of the faulty test values; and identifying elements of the system that are likely to contain the faults of the system by performing a partial intersection on the sets of candidate faulty elements wherein only elements associated with at least a predetermined number of faulty test values are selected.
Claim 2
Independent Claim
153 words
A method for identifying elements of a faulty system, that are likely to contain the faults of the system, based on a set of test vectors output from the system wherein each test vector contains a set of test values, the method comprising the steps of: comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; identifying a set of candidate faulty elements for each of the faulty test values; and identifying elements of the system that are likely to contain the faults of the system by performing a partial intersection on the sets of candidate faulty elements wherein only elements associated with at least a predetermined number of faulty test values are selected.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein the system is a circuit formed on a chip, the elements of the system are logic gates, and the test values are test bits.
Claim 4
Dependent Claim
97 words
The method of claim 1, wherein said step of identifying elements that are likely to contain faults by performing a partial intersection on the sets of candidate faulty elements comprises the steps of: selecting a threshold fault count; determining a fault count for each candidate faulty element, said fault count being representative of the number of occurrences of each respective faulty element within all sets of candidate faulty elements associated with all faulty values; and identifying all elements which have a fault count greater than the selected threshold fault count as the elements likely to contain faults.
Claim 5
Dependent Claim
26 words
The method of claim 3, wherein said selected threshold fault count identifies the threshold in relation to a fault count having a highest degree of intersection.
Claim 6
Dependent Claim
51 words
The method of claim 3, wherein the steps of determining a fault count for each candidate faulty element and identifying all elements which have a fault count greater than the selected threshold are first performed on faults associated with individual test vectors then performed on faults associated with different test vectors.
Claim 7
Independent Claim
155 words
An apparatus for identifying elements of a faulty system, that are likely to contain the faults of the system, based on a set of test vectors output from the system wherein each test vector contains a set of test values, the apparatus comprising: a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; a device for identifying a set of candidate faulty elements for each of the faulty test values; and a device for identifying elements of the system that are likely to contain faults by performing a partial intersection on the sets of candidate faulty elements wherein only elements associated with at least a predetermined number of faulty test values are selected.
Claim 8
Independent Claim
155 words
An apparatus for identifying elements of a faulty system, that are likely to contain the faults of the system, based on a set of test vectors output from the system wherein each test vector contains a set of test values, the apparatus comprising: a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; a device for identifying a set of candidate faulty elements for each of the faulty test values; and a device for identifying elements of the system that are likely to contain faults by performing a partial intersection on the sets of candidate faulty elements wherein only elements associated with at least a predetermined number of faulty test values are selected.
Claim 9
Dependent Claim
30 words
The apparatus of claim 6, wherein the system is a circuit formed on a chip, the elements of the system are logic gates, and the test values are test bits.
Claim 10
Dependent Claim
101 words
The apparatus of claim 6, wherein said device for identifying elements likely to contain faults by performing a partial intersection on the sets of candidate faulty elements comprises: a device for selecting a threshold fault count; a device for determining a fault count for each candidate faulty element, said fault count being representative of the number of occurrences of each respective faulty element within all sets of candidate faulty elements associated with all faulty values; and a device for identifying all elements which have a fault count greater than the selected threshold fault count as the elements likely to contain faults.
Claim 11
Dependent Claim
26 words
The apparatus of claim 8, wherein said selected threshold fault count identifies the threshold in relation to a fault count having a highest degree of intersection.
Claim 12
Dependent Claim
49 words
The apparatus of claim 8, wherein the devices for determining a fault count for each candidate faulty element and for identifying all elements which have a fault count greater than the selected threshold operate on faults associated with individual test vectors then on faults associated with different test vectors.
Claim 13
Independent Claim
161 words
A method for identifying elements of a faulty system, that are likely to contain the faults of the system, based on a set of test vectors output from the system wherein each test vector contains a set of test values, the method comprising the steps of: providing a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; providing a device for identifying a set of candidate faulty elements for each of the faulty test values; and providing a device for identifying elements of the system that are likely to contain faults by performing a partial intersection on the sets of candidate faulty elements wherein only elements associated with at least a predetermined number of faulty test values are selected.
Claim 14
Independent Claim
161 words
A method for identifying elements of a faulty system, that are likely to contain the faults of the system, based on a set of test vectors output from the system wherein each test vector contains a set of test values, the method comprising the steps of: providing a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; providing a device for identifying a set of candidate faulty elements for each of the faulty test values; and providing a device for identifying elements of the system that are likely to contain faults by performing a partial intersection on the sets of candidate faulty elements wherein only elements associated with at least a predetermined number of faulty test values are selected.
Claim 15
Dependent Claim
30 words
The method of claim 11, wherein the system is a circuit formed on a chip, the elements of the system are logic gates, and the test values are test bits.
Claim 16
Dependent Claim
111 words
The method of claim 11, wherein said step of providing a device for identifying elements likely to contain faults by performing a partial intersection on the sets of candidate faulty elements comprises the steps of: providing a device for selecting a threshold fault count; providing a device for determining a fault count for each candidate faulty element, said fault count being representative of the number of occurrences of each respective faulty element within all sets of candidate faulty elements associated with all faulty values; and providing a device for identifying all elements which have a fault count greater than the selected threshold fault count as the elements likely to contain faults.
Claim 17
Dependent Claim
26 words
The method of claim 13, wherein said selected threshold fault count identifies the threshold in relation to a fault count having a highest degree of intersection.
Claim 18
Dependent Claim
49 words
The method of claim 13, wherein the devices for determining a fault count for each candidate faulty element and for identifying all elements which have a fault count greater than the selected threshold operate on faults associated with individual test vectors then on faults associated with different test vectors.
Claim 19
Dependent Claim
184 words
A test method for testing an electronic system provided on a chip and having a plurality of elements, said method comprising the steps of: receiving a set of test vectors output from the system; comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; identifying a set of candidate faulty elements for each of the faulty test values; and identifying elements of the system that are likely to contain faults based on the sets of candidate faulty elements by performing a partial intersection on the sets of candidate faulty element associated with faulty test values wherein only elements which are associated with at least a predetermined number of faulty values are selected; and determining the physical location of the elements likely to contain faults within the chip by employing a software tool capable of identifying the location on a chip of one or more elements.
Claim 20
Dependent Claim
184 words
A test method for testing an electronic system provided on a chip and having a plurality of elements, said method comprising the steps of: receiving a set of test vectors output from the system; comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; identifying a set of candidate faulty elements for each of the faulty test values; and identifying elements of the system that are likely to contain faults based on the sets of candidate faulty elements by performing a partial intersection on the sets of candidate faulty element associated with faulty test values wherein only elements which are associated with at least a predetermined number of faulty values are selected; and determining the physical location of the elements likely to contain faults within the chip by employing a software tool capable of identifying the location on a chip of one or more elements.
Claim 21
Dependent Claim
30 words
The method of claim 16, wherein the system is a circuit formed on a chip, the elements of the system are logic gates, and the test values are test bits.
Claim 22
Dependent Claim
88 words
The method of claim 16, wherein the step of performing a partial intersection on the sets of candidate faulty elements comprises the steps of: selecting a threshold fault count; determining a fault count for each candidate faulty element, said fault count being representative of the number of occurrences of each respective faulty element within all sets of candidate faulty elements associated with all faulty values; and identifying all elements which have a fault count greater than the selected threshold fault count as the elements likely to contain faults.
Claim 23
Dependent Claim
26 words
The method of claim 18, wherein said selected threshold fault count identifies the threshold in relation to a fault count having a highest degree of intersection.
Claim 24
Dependent Claim
51 words
The method of claim 18, wherein the steps of determining a fault count for each candidate faulty element and identifying all elements which have a fault count greater than the selected threshold are first performed on faults associated with individual test vectors then performed on faults associated with different test vectors.
Claim 25
Dependent Claim
196 words
A test apparatus for testing an electronic system provided on a chip and having a plurality of elements, said apparatus comprising: a device for receiving a set of test vectors output from the system; a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; a device for identifying a set of candidate faulty elements for each of the faulty test values; and a device for identifying elements of the system that are likely to contain faults based on the sets of candidate faulty elements by performing a partial intersection on the sets of candidate faulty elements associate with faulty test values wherein only elements which are associated with at least a predetermined number of faulty values are selected; and a device for determining the physical location of the elements likely to contain faults within the chip by employing a software tool capable of identifying the location on a chip of one or more elements.
Claim 26
Dependent Claim
196 words
A test apparatus for testing an electronic system provided on a chip and having a plurality of elements, said apparatus comprising: a device for receiving a set of test vectors output from the system; a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; a device for identifying a set of candidate faulty elements for each of the faulty test values; and a device for identifying elements of the system that are likely to contain faults based on the sets of candidate faulty elements by performing a partial intersection on the sets of candidate faulty elements associate with faulty test values wherein only elements which are associated with at least a predetermined number of faulty values are selected; and a device for determining the physical location of the elements likely to contain faults within the chip by employing a software tool capable of identifying the location on a chip of one or more elements.
Claim 27
Dependent Claim
30 words
The apparatus of claim 21, wherein the system is a circuit formed on a chip, the elements of the system are logic gates, and the test values are test bits.
Claim 28
Dependent Claim
94 words
The apparatus of claim 21, wherein the device for performing a partial intersection on the sets of candidate faulty elements comprises: a device for selecting a threshold fault count; a device for determining a fault count for each candidate faulty element, said fault count being representative of the number of occurrences of each respective faulty element within all sets of candidate faulty elements associated with all faulty values; and a device for identifying all elements which have a fault count greater than the selected threshold fault count as the elements likely to contain faults.
Claim 29
Dependent Claim
26 words
The apparatus of claim 21, wherein said selected threshold fault count identifies the threshold in relation to a fault count having a highest degree of intersection.
Claim 30
Dependent Claim
51 words
The apparatus of claim 21, wherein the devices for determining a fault count for each candidate faulty element and identifying all elements which have a fault count greater than the selected threshold are first performed on faults associated with individual test vectors then performed on faults associated with different test vectors.
Claim 31
Independent Claim
203 words
A method for testing an electronic system provided on a chip and having a plurality of elements, said method comprising the steps of: providing a device for receiving a set of test vectors output from the system; providing a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; providing a device for identifying a set of candidate faulty elements for each of the faulty test values; and providing a device for identifying elements of the system that are likely to contain faults based on the sets of candidate faulty elements by performing a partial intersection on the sets of candidate faulty elements associated with faulty test values wherein only elements which are associated with at least a predetermined number of faulty values are selected; and providing a device for determining the physical location of the elements likely to contain faults within the chip by employing a software tool capable of identifying the location on a chip of one or more elements.
Claim 32
Independent Claim
203 words
A method for testing an electronic system provided on a chip and having a plurality of elements, said method comprising the steps of: providing a device for receiving a set of test vectors output from the system; providing a device for comparing the output test vectors with an expected set of output test vectors to identify faulty test values, with any differences between the output test vectors and corresponding expected test vectors indicating a failure of the test and indicating that at least one element of the system is faulty; providing a device for identifying a set of candidate faulty elements for each of the faulty test values; and providing a device for identifying elements of the system that are likely to contain faults based on the sets of candidate faulty elements by performing a partial intersection on the sets of candidate faulty elements associated with faulty test values wherein only elements which are associated with at least a predetermined number of faulty values are selected; and providing a device for determining the physical location of the elements likely to contain faults within the chip by employing a software tool capable of identifying the location on a chip of one or more elements.
Claim 33
Dependent Claim
30 words
The method of claim 26, wherein the system is a circuit formed on a chip, the elements of the system are logic gates, and the test values are test bits.
Claim 34
Dependent Claim
104 words
The method of claim 26, wherein the steps of providing a device for performing a partial intersection on the sets of candidate faulty elements comprises the steps of: providing a device for selecting a threshold fault count; providing a device for determining a fault count for each candidate faulty element, said fault count being representative of the number of occurrences of each respective faulty element within all sets of candidate faulty elements associated with all faulty values; and providing a device for identifying all elements which have a fault count greater than the selected threshold fault count as the elements likely to contain faults.
Claim 35
Dependent Claim
26 words
The method of claim 26, wherein said selected threshold fault count identifies the threshold in relation to a fault count having a highest degree of intersection.
Claim 36
Dependent Claim
51 words
The method of claim 28, wherein the devices for determining a fault count for each candidate faulty element and identifying all elements which have a fault count greater than the selected threshold are first performed on faults associated with individual test vectors then performed on faults associated with different test vectors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |