Patent US5570319A successfully refreshed from Google Patents.
US5570319A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Embedded access trees for memory arrays
Assignee: Sun Microsystems Inc
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Filing: 1995-08-31
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Granted: 1996-10-29
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Expires: 2015-08-31
Abstract
Abstract An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements.
Inventors
- 👤 Mark R. Santoro
- 👤 Lee S. Tavrow
- 👤 Gary W. Bewick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C7/00; G11C7/18; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
52 words
A circuit comprising: a select line; a bit line coupled to a memory cell; a bipolar transistor having a base coupled to the bit line; and a passive element coupled between the base of the bipolar transistor and the select line to activate the bipolar transistor when the select line is selected.
Claim 2
Dependent Claim
52 words
A circuit comprising: a select line; a bit line coupled to a memory cell; a bipolar transistor having a base coupled to the bit line; and a passive element coupled between the base of the bipolar transistor and the select line to activate the bipolar transistor when the select line is selected.
Claim 3
Dependent Claim
12 words
The circuit of claim 1, wherein the passive clement is a resistor.
Claim 4
Dependent Claim
13 words
The circuit of claim 1, wherein the passive element is a first transistor.
Claim 5
Dependent Claim
32 words
The circuit of claim 3, wherein the first transistor has a control electrode coupled to a write bit line for deactivating the bipolar transistor during a write operation to the memory cell.
Claim 6
Dependent Claim
30 words
The circuit of claim 1, wherein the bipolar transistor acts as a sense amplifier for sensing the data on the bit line during a read operation of the memory cell.
Claim 7
Dependent Claim
29 words
The circuit of claim 1, further comprising a precharge circuit coupled to the bit line for precharging the bit line prior to a read operation of the memory cell.
Claim 8
Dependent Claim
18 words
The circuit of claim 6, wherein the precharge circuit comprises a precharge transistor coupled to the bit line.
Claim 9
Dependent Claim
30 words
The circuit of claim 7, further comprising a write bit line coupled to the precharge transistor configured to deactivate the precharge transistor during a write operation to the memory cell.
Claim 10
Dependent Claim
25 words
The circuit of claim 1, further comprising a pull up circuit to pull up the bit line after a write operation of the memory cell.
Claim 11
Dependent Claim
38 words
The circuit of claim 9, wherein the pull up circuit comprises a pull up transistor coupled between the bit line and a control circuit for deactivating the pull up transistor during a write operation to the memory cell.
Claim 12
Dependent Claim
30 words
The circuit of claim 1, further comprising a pull down transistor, coupled to the bit line, for pulling down the bit line during a write operation to the memory cell.
Claim 13
Dependent Claim
28 words
The circuit of claim 1, further comprising a bank select transistor, coupled to the bit line, configured to select a bank of memory cells including the memory cell.
Claim 14
Dependent Claim
23 words
The circuit of claim 1, wherein the select select line is used to activate a subarray of memory cells including the memory cell.
Claim 15
Dependent Claim
61 words
The circuit of claim 1, further comprising: a differential bit line coupled to the memory cell; a second bipolar transistor having a second base coupled to the differential bit fine; and a second passive element coupled between the second base of the second bipolar transistor and the select line to activate the second bipolar transistor when the select line is selected.
Claim 16
Dependent Claim
34 words
The circuit of claim 1, wherein a first electrode of the bipolar transistor is coupled to a power supply and a second electrode of the bipolar transistor is coupled to a global bit line.
Claim 17
Independent Claim
65 words
A method of providing a circuit, the method comprising the steps of: providing a select line; providing a bit line coupled to a memory cell; providing a bipolar transistor having a base coupled to the bit line; and providing a passive element coupled between the base of the bipolar transistor and the select line to activate the bipolar transistor when the select line is selected.
Claim 18
Independent Claim
65 words
A method of providing a circuit, the method comprising the steps of: providing a select line; providing a bit line coupled to a memory cell; providing a bipolar transistor having a base coupled to the bit line; and providing a passive element coupled between the base of the bipolar transistor and the select line to activate the bipolar transistor when the select line is selected.
Claim 19
Dependent Claim
67 words
The method of claim 16, further comprising the steps of: providing a differential bit line coupled to the memory cell; providing a second bipolar transistor having a second base coupled to the differential bit line; and providing a second passive element coupled between the second base of the second bipolar transistor and the select line to activate the second bipolar transistor when the select line is selected.
Claim 20
Independent Claim
58 words
A method of operating a memory array, comprising the steps of: selecting a select line; activating a bipolar transistor through a passive element coupled between the select line and a base of the bipolar transistor; activating a bit line in response to the step of activating the bipolar transistor; and reading a memory cell on the bit line.
Claim 21
Independent Claim
58 words
A method of operating a memory array, comprising the steps of: selecting a select line; activating a bipolar transistor through a passive element coupled between the select line and a base of the bipolar transistor; activating a bit line in response to the step of activating the bipolar transistor; and reading a memory cell on the bit line.
References Cited (Backward Citations)
US5132930A
Cited
US5295111A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |