EEPROM devices with smaller cell size

Claim 1

An array of electrically erasable and programmable read-only memory cells formed on a semiconductor substrate, the array comprising: a plurality of parallel bit lines formed in the substrate; a plurality of spaced-apart field oxide regions formed on the substrate in rows and columns so that a column of field oxide regions is formed between each adjacent pair of bit lines, each field oxide region having sidewalls; a plurality of channel regions defined in the substrate between each adjacent pair of bit lines so that a channel region is defined between each adjacent pair of field oxide regions in each column of field oxide regions formed between each adjacent pair of bit lines; a plurality of first dielectric regions formed on the plurality of channel regions so that each first dielectric region is formed over a corresponding channel region; a plurality of floating gate regions formed over the plurality of first dielectric regions so that each floating gate region is formed over a corresponding first dielectric region and a part of each adjacent field oxide region, each floating gate region having a a sidewall substantially vertically aligned with a sidewall of each of the adjacent field oxide regions that are partially covered by said each floating gate region; a plurality of second dielectric regions formed over the plurality of floating gate regions so that each second dielectric region is formed over a corresponding floating gate region; and a plurality of control gate regions formed over the plurality of second dielectric regions so that each control gate region is formed over a corresponding second dielectric region.