Patent US5569625A successfully refreshed from Google Patents.
US5569625A
Expired / Lapsed
US
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Process for manufacturing a plural stacked leadframe semiconductor device
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1994-11-22
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Granted: 1996-10-29
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Expires: 2014-11-22
Abstract
Abstract A semiconductor process includes a stage, a semiconductor chip which is mounted on the stage, a plurality of electrode members which are wire bonded to the semiconductor chip, where a first gap is formed between the stage and one electrode member and a second gap is formed between two electrode members, a plurality of leads including inner leads which are wire bonded to at least one of the semiconductor chip and the electrode members and electrically connected thereto, and a resin package which encapsulates the semiconductor chip, the stage, the electrode members and the inner leads by a resin. The resin fills the first and second gaps, so that the stage and the one electrode member are isolated and the two electrode members are isolated.
Inventors
- 👤 Yoshiyuki Yoneda
- 👤 Kazuto Tsuji
- 👤 Junichi Kasai
- 👤 Hideharu Sakoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:21
CPC Classifications
H; H10; H10W; H10W40/00; H10W40/70; H10W40/77; H10W40/778; H10W70/00; H10W70/40; H10W70/421; H10W70/442; H10W74/00; H10W74/01; H10W74/016; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/731; H10W90/732; H10W90/736; H10W90/751; H10W90/754; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
211 words
A method of producing a semiconductor device comprising the steps of: (a) forming a lead frame assembly which includes a plurality of lead frames which are spaced apart from one another and stacked, said lead frames including a first lead frame having leads formed thereon, a second lead frame arranged below the first lead frame and having a stage on which a semiconductor chip is mounted, said stage separated from said leads by a first gap, and third lead frames arranged below the second lead frame by second gaps and having electrode members; (b) connecting wires between the semiconductor chip and the first lead frame, between the semiconductor chip and the third lead frames, and between the third leads frames and the first lead frame by a wire bonding; (c) forming a resin package by a resin which fills the first and second gaps and which encapsulates the semiconductor chip, the stage, the electrode members and inner leads of the leads; and (d) cutting off unwanted parts of the lead frame assembly located outside the resin package; wherein step (a) interposes spacers only in said unwanted parts of the lead frame assembly so that the first and second lead frames and the third lead frames are spaced apart from one another.
Claim 2
Independent Claim
211 words
A method of producing a semiconductor device comprising the steps of: (a) forming a lead frame assembly which includes a plurality of lead frames which are spaced apart from one another and stacked, said lead frames including a first lead frame having leads formed thereon, a second lead frame arranged below the first lead frame and having a stage on which a semiconductor chip is mounted, said stage separated from said leads by a first gap, and third lead frames arranged below the second lead frame by second gaps and having electrode members; (b) connecting wires between the semiconductor chip and the first lead frame, between the semiconductor chip and the third lead frames, and between the third leads frames and the first lead frame by a wire bonding; (c) forming a resin package by a resin which fills the first and second gaps and which encapsulates the semiconductor chip, the stage, the electrode members and inner leads of the leads; and (d) cutting off unwanted parts of the lead frame assembly located outside the resin package; wherein step (a) interposes spacers only in said unwanted parts of the lead frame assembly so that the first and second lead frames and the third lead frames are spaced apart from one another.
Claim 3
Dependent Claim
26 words
The method as claimed in claim 1, wherein said step (c) molds the resin package using dies which include positioning means for positioning the electrode members.
Claim 4
Dependent Claim
33 words
The method as claimed in claim 2, wherein said step (a) forms a lead frame assembly having positioning parts which are engaged by the positioning means of the dies in said step (c).
Claim 5
Dependent Claim
68 words
The method as claimed in claim 1, wherein said step (a) forms a lead frame assembly in which each third lead frame has an outer frame and the electrode members supported on the outer frame via support bars, and said step (c) molds the resin package using dies which are located on the inside of the outer frame and put between the support bars to prevent resin leakage.
Claim 6
Dependent Claim
32 words
The method as claimed in claim 1, which further comprises the step of: (e) plating surfaces of at least one of the first and second lead frames to enable wire bonding thereon.
Claim 7
Dependent Claim
23 words
The method as claimed in claim 5, wherein said (e) plates a metal selected from a group consisting of Pd, Ag and Au.
Claim 8
Dependent Claim
69 words
A method as claimed in claim 1, wherein said plurality of lead frames are stacked with spacers, a first spacer providing said first gap between said first and second lead frames and second spacers formed between said second and third lead frames and between third lead frames and wherein said resin, which fills said first and second gaps, isolates said first, second and third lead frames from one another.
Claim 9
Independent Claim
240 words
A method of producing a semiconductor device comprising the steps of: (a) forming a lead frame assembly which includes a plurality of lead frames which are spaced apart from one another and stacked, said lead frames including a first lead frame having leads formed thereon, a second lead frame arranged below the first lead frame and having a stage on which a semiconductor chip is mounted, said stage separated from said leads by a first gap, a third lead frame arranged below the second lead frame by a second gap and having first electrode members, and a fourth lead frame arranged below the third lead frame by a third gap and having second electrode members; (b) connecting wires between the semiconductor chip and the first lead frame, between the semiconductor chip and the third lead frame, between the semiconductor chip and the fourth lead frame, between the third lead frame and the first lead frame and between the fourth lead frame and the first lead frame by a wire bonding; (c) forming a resin package by a resin which fills the first, second and third gaps and which encapsulates the semiconductor chip, the stage, the first and second electrode members and inner leads of the leads, wherein said stage and first electrode members are isolated and said first and second electrode members are isolated; and (d) cutting off unwanted parts of the lead frame assembly located outside the resin package.
Claim 10
Independent Claim
240 words
A method of producing a semiconductor device comprising the steps of: (a) forming a lead frame assembly which includes a plurality of lead frames which are spaced apart from one another and stacked, said lead frames including a first lead frame having leads formed thereon, a second lead frame arranged below the first lead frame and having a stage on which a semiconductor chip is mounted, said stage separated from said leads by a first gap, a third lead frame arranged below the second lead frame by a second gap and having first electrode members, and a fourth lead frame arranged below the third lead frame by a third gap and having second electrode members; (b) connecting wires between the semiconductor chip and the first lead frame, between the semiconductor chip and the third lead frame, between the semiconductor chip and the fourth lead frame, between the third lead frame and the first lead frame and between the fourth lead frame and the first lead frame by a wire bonding; (c) forming a resin package by a resin which fills the first, second and third gaps and which encapsulates the semiconductor chip, the stage, the first and second electrode members and inner leads of the leads, wherein said stage and first electrode members are isolated and said first and second electrode members are isolated; and (d) cutting off unwanted parts of the lead frame assembly located outside the resin package.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |