Method for rearranging instruction sequence in risc architecture

Claim 1

A method of rearranging RISC (reduced instruction set computer) program instructions which together perform a specific task and which include a branch instruction and which constitute an instruction block, comprising the following steps implemented in a computer: (a) determining, in said computer, which RISC instruction or instructions must be implemented before another RISC instruction is carried out; (b) determining, in said computer, which RISC instruction must not be implemented before a RISC instruction or instructions is carried out; (c) determining, in said computer, if said branch instruction is in a predetermined position in said instruction block; (d) listing, in said computer, a plurality of instruction sequences which satisfy requirements determined by steps (a), (b) and (c), each one of said plurality of instruction sequences performing said specific task; and (e) selecting, in said computer, one instruction sequence of a plurality of listed instruction sequences to implement said specific task in a shortest time.

Claim 2

A method of rearranging RISC (reduced instruction set computer) program instructions which together perform a specific task and which include a branch instruction and which constitute an instruction block, comprising the following steps implemented in a computer: (a) determining, in said computer, which RISC instruction or instructions must be implemented before another RISC instruction is carried out; (b) determining, in said computer, which RISC instruction must not be implemented before a RISC instruction or instructions is carried out; (c) determining, in said computer, if said branch instruction is in a predetermined position in said instruction block; (d) listing, in said computer, a plurality of instruction sequences which satisfy requirements determined by steps (a), (b) and (c), each one of said plurality of instruction sequences performing said specific task; and (e) selecting, in said computer, one instruction sequence of a plurality of listed instruction sequences to implement said specific task in a shortest time.

Claim 5

A method of rearranging RISC (reduced instruction set computer) program instructions which together perform a specific task and which include a branch instruction and which constitute an instruction block, comprising the following steps implemented in a computer: (a) determining, in said computer, which operand or operands must be defined before each of said RISC instructions is carried out; (b) determining, in said computer, which RISC instruction destroys an operand to be operated on by another RISC instruction; (c) determining, in said computer, if said branch instruction is in a predetermined position in said instruction block; (d) listing, in said computer, a plurality of instruction sequences which satisfy requirements determined by steps (a), (b) and (c), each one of said plurality of instruction sequences performing said specific task; and (e) selecting, in said computer, one instruction sequence of a plurality of listed instruction sequences to implement said specific task in a shortest time.

Claim 6

A method of rearranging RISC (reduced instruction set computer) program instructions which together perform a specific task and which include a branch instruction and which constitute an instruction block, comprising the following steps implemented in a computer: (a) determining, in said computer, which operand or operands must be defined before each of said RISC instructions is carried out; (b) determining, in said computer, which RISC instruction destroys an operand to be operated on by another RISC instruction; (c) determining, in said computer, if said branch instruction is in a predetermined position in said instruction block; (d) listing, in said computer, a plurality of instruction sequences which satisfy requirements determined by steps (a), (b) and (c), each one of said plurality of instruction sequences performing said specific task; and (e) selecting, in said computer, one instruction sequence of a plurality of listed instruction sequences to implement said specific task in a shortest time.