Patent US5568067A successfully refreshed from Google Patents.
US5568067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Configurable XNOR/XOR element
Assignee: Advanced Micro Devices Inc
•
Filing: 1995-06-30
•
Granted: 1996-10-22
•
Expires: 2015-06-30
Abstract
Abstract A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output.
Inventors
- 👤 Mark W. McDermott
- 👤 John E. Turner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
337 words
A configurable XNOR/XOR logic element receiving A and B inputs and providing a Y output, comprising: (a) first parallel transistors including a /B-input p-transistor in parallel with a B-input p-transistor; and (b) second parallel transistors including an A-input p-transistor in parallel with a /A-input p-transistor; (c) the first and second parallel transistors being selectively intercoupled by a first coupling circuit; (d) third parallel transistors including an A-input n-transistor in parallel with a /A-input n-transistor; and (e) fourth parallel transistors including an B-input n-transistor in parallel with a /B-input n-transistor; (f) the third and fourth parallel transistors being selectively intercoupled by a second coupling circuit; (g) the A-input p-transistor of the second parallel transistors being coupled in series to the A-input n-transistor of the third parallel transistors to define a first output node, and the /A-input p-transistor of the second parallel transistors being coupled in series to the /A-input n-transistor of the third parallel transistors to define a second output node, the first and second output nodes being coupled to provide the Y output; (h) the first and second coupling circuits being controlled by a C input such that; (i) if the C input is asserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively cross-coupled to the /A-input and A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively cross-coupled to the /B-input and B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XNOR gate with a corresponding Y output; or (j) if the C input is deasserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively series-coupled to the A-input and /A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively series-coupled to the B-input and /B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XOR gate with a corresponding Y output.
Claim 2
Dependent Claim
337 words
A configurable XNOR/XOR logic element receiving A and B inputs and providing a Y output, comprising: (a) first parallel transistors including a /B-input p-transistor in parallel with a B-input p-transistor; and (b) second parallel transistors including an A-input p-transistor in parallel with a /A-input p-transistor; (c) the first and second parallel transistors being selectively intercoupled by a first coupling circuit; (d) third parallel transistors including an A-input n-transistor in parallel with a /A-input n-transistor; and (e) fourth parallel transistors including an B-input n-transistor in parallel with a /B-input n-transistor; (f) the third and fourth parallel transistors being selectively intercoupled by a second coupling circuit; (g) the A-input p-transistor of the second parallel transistors being coupled in series to the A-input n-transistor of the third parallel transistors to define a first output node, and the /A-input p-transistor of the second parallel transistors being coupled in series to the /A-input n-transistor of the third parallel transistors to define a second output node, the first and second output nodes being coupled to provide the Y output; (h) the first and second coupling circuits being controlled by a C input such that; (i) if the C input is asserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively cross-coupled to the /A-input and A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively cross-coupled to the /B-input and B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XNOR gate with a corresponding Y output; or (j) if the C input is deasserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively series-coupled to the A-input and /A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively series-coupled to the B-input and /B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XOR gate with a corresponding Y output.
Claim 3
Dependent Claim
102 words
The XNOR/XOR logic element of claim 1, wherein the first coupling circuit comprises: (a) first and second C-input p-transistors respectively series-coupled between (i) the /B-input p-transistor of the first parallel transistors and the A-input of the second parallel transistors, and (ii) the B-input p-transistor of the first parallel transistors and the /A-input of the second parallel transistors; and (b) third and fourth /C-input p-transistors respectively cross-coupled between (i) the /B-input p-transistor of the first parallel transistors and the /A-input of the second parallel transistors, and (ii) the B-input p-transistor of the first parallel transistors and the A-input of the second parallel transistors.
Claim 4
Dependent Claim
102 words
The XNOR/XOR logic element of claim 1, wherein the second coupling circuit comprises: (a) first and second /C-input n-transistors respectively series-coupled between (i) the A-input n-transistor of the third parallel transistors and the B-input of the fourth parallel transistors, and (ii) the /A-input n-transistor of the third parallel transistors and the /B-input of the fourth parallel transistors; and (b) third and fourth C-input n-transistors respectively cross-coupled between (i) the A-input n-transistor of the third parallel transistors and the /B-input of the fourth parallel transistors, and (ii) the /A-input n-transistor of the third parallel transistors and the B-input of the fourth parallel transistors.
Claim 5
Dependent Claim
55 words
The XNOR/XOR logic element of claim 1, wherein: (a) the A and B inputs to the logic element are the A and B inputs to a full adder, and the C input is the carry-in to the full adder; and (b) the Y output is the complement of the sum output of the full adder.
Claim 6
Dependent Claim
357 words
In an array of spare gates incorporated into an integrated circuit, a plurality of configurable XNOR/XOR logic elements each receiving A and B inputs and providing a Y output, each XNOR/XOR logic element comprising: (a) first parallel transistors including a /B-input p-transistor in parallel with a B-input p transistor; and (b) second parallel transistors including an A-input p-transistor in parallel with a /A-input p transistor; (c) the first and second parallel transistors being selectively intercoupled by a first coupling circuit; (d) third parallel transistors including an A-input n-transistor in parallel with a /A-input n-transistor; and (e) fourth parallel transistors including an B-input n-transistor in parallel with a /B-input n-transistor; (f) the third and fourth parallel transistors being selectively intercoupled by a second coupling circuit; (g) the A-input p-transistor of the second parallel transistors being coupled in series to the A-input n-transistor of the third parallel transistors to define a first output node, and the /A-input p-transistor of the second parallel transistors being coupled in series to the /A-input n-transistor of the third parallel transistors to define a second output node, the first and second output nodes being coupled to provide the Y output; (h) the first and second coupling circuits being controlled by a C input such that; (i) if the C input is asserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively cross-coupled to the /A-input and A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively cross-coupled to the /B-input and B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XNOR gate with a corresponding Y output; or (j) if the C input is deasserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively series-coupled to the A-input and /A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively series-coupled to the B-input and /B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XOR gate with a corresponding Y output.
Claim 7
Dependent Claim
357 words
In an array of spare gates incorporated into an integrated circuit, a plurality of configurable XNOR/XOR logic elements each receiving A and B inputs and providing a Y output, each XNOR/XOR logic element comprising: (a) first parallel transistors including a /B-input p-transistor in parallel with a B-input p transistor; and (b) second parallel transistors including an A-input p-transistor in parallel with a /A-input p transistor; (c) the first and second parallel transistors being selectively intercoupled by a first coupling circuit; (d) third parallel transistors including an A-input n-transistor in parallel with a /A-input n-transistor; and (e) fourth parallel transistors including an B-input n-transistor in parallel with a /B-input n-transistor; (f) the third and fourth parallel transistors being selectively intercoupled by a second coupling circuit; (g) the A-input p-transistor of the second parallel transistors being coupled in series to the A-input n-transistor of the third parallel transistors to define a first output node, and the /A-input p-transistor of the second parallel transistors being coupled in series to the /A-input n-transistor of the third parallel transistors to define a second output node, the first and second output nodes being coupled to provide the Y output; (h) the first and second coupling circuits being controlled by a C input such that; (i) if the C input is asserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively cross-coupled to the /A-input and A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively cross-coupled to the /B-input and B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XNOR gate with a corresponding Y output; or (j) if the C input is deasserted, then (a) the /B-input and B-input p-transistors of the first parallel transistors are respectively series-coupled to the A-input and /A-input p-transistors of the second parallel transistors, and (b) the A-input and /A-input n-transistors of the third parallel transistors are respectively series-coupled to the B-input and /B-input n-transistors of the fourth parallel transistors, thereby configuring the XNOR/XOR logic element as an XOR gate with a corresponding Y output.
Claim 8
Dependent Claim
102 words
The XNOR/XOR logic element of claim 5, wherein the first coupling circuit comprises: (a) first and second C-input p-transistors respectively series-coupled between (i) the /B-input p-transistor of the first parallel transistors and the A-input of the second parallel transistors, and (ii) the B-input p-transistor of the first parallel transistors and the /A-input of the second parallel transistors; and (b) third and fourth /C-input p-transistors respectively cross-coupled between (i) the /B-input p-transistor of the first parallel transistors and the /A-input of the second parallel transistors, and (ii) the B-input p-transistor of the first parallel transistors and the A-input of the second parallel transistors.
Claim 9
Dependent Claim
102 words
The XNOR/XOR logic element of claim 5, wherein the second coupling circuit comprises: (a) first and second /C-input n-transistors respectively series-coupled between (i) the A-input n-transistor of the third parallel transistors and the B-input of the fourth parallel transistors, and (ii) the /A-input n-transistor of the third parallel transistors and the /B-input of the fourth parallel transistors; and (b) third and fourth C-input n-transistors respectively cross-coupled between (i) the A-input n-transistor of the third parallel transistors and the /B-input of the fourth parallel transistors, and (ii) the /A-input n-transistor of the third parallel transistors and the B-input of the fourth parallel transistors.
Claim 10
Dependent Claim
25 words
The XNOR/XOR logic element of claim 1, wherein the state of the C input as asserted or deasserted is determined at the time of fabrication.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |