Method of fabricating self-aligned contact trench DMOS transistors

Claim 1

A method of fabricating a trench DMOS transistor structure having a source and a body and a contact to the source and body of the transistor structure that is self-aligned to a trench formed to isolate the transistor structure, the method comprising: forming a silicon dioxide layer on an underlying layer of N-type epitaxial silicon; forming a nitride layer on the silicon dioxide layer, the nitride layer having an upper surface; forming a low temperature oxide (LTO) layer on the nitride layer to define an LTO/nitride/silicon dioxide (ONO) sandwich; defining a trench mask on the LTO layer to expose regions of the LTO layer; etching the ONO sandwich to expose regions of the N-type epitaxial layer underlying the exposed regions of the LTO layer; etching the exposed regions of the N-type epitaxial layer to define trenches therein; forming silicon dioxide on exposed surfaces of the trenches; depositing a polysilicon layer to fill the trenches; etching the polysilicon layer to define polysilicon gate regions within the trenches, each polysilicon gate region having an upper surface that is higher than the upper surface of said nitride layer; removing the LTO layer; removing the nitride layer; implanting P-dopant to form a region of P-type conductivity between the trenches; defining an N+ source mask and using the N+ source mask to implant N-dopant to define N+ source regions adjacent to the trenches; oxidizing the polysilicon gate regions to form oxide pads on the upper surface of the polysilicon gate regions and oxide spacers on exposed sidewalls of the polysilicon gate regions such that the oxide spacers extend over the N+ source regions; implanting P-dopant to form P+ body ohmic contact regions between the N+ source regions; and forming a conductive layer over the oxide pads and the oxide spacers for contact with the P+ body ohmic contact regions.

Claim 2

A method of fabricating a trench DMOS transistor structure having a source and a body and a contact to the source and body of the transistor structure that is self-aligned to a trench formed to isolate the transistor structure, the method comprising: forming a silicon dioxide layer on an underlying layer of N-type epitaxial silicon; forming a nitride layer on the silicon dioxide layer, the nitride layer having an upper surface; forming a low temperature oxide (LTO) layer on the nitride layer to define an LTO/nitride/silicon dioxide (ONO) sandwich; defining a trench mask on the LTO layer to expose regions of the LTO layer; etching the ONO sandwich to expose regions of the N-type epitaxial layer underlying the exposed regions of the LTO layer; etching the exposed regions of the N-type epitaxial layer to define trenches therein; forming silicon dioxide on exposed surfaces of the trenches; depositing a polysilicon layer to fill the trenches; etching the polysilicon layer to define polysilicon gate regions within the trenches, each polysilicon gate region having an upper surface that is higher than the upper surface of said nitride layer; removing the LTO layer; removing the nitride layer; implanting P-dopant to form a region of P-type conductivity between the trenches; defining an N+ source mask and using the N+ source mask to implant N-dopant to define N+ source regions adjacent to the trenches; oxidizing the polysilicon gate regions to form oxide pads on the upper surface of the polysilicon gate regions and oxide spacers on exposed sidewalls of the polysilicon gate regions such that the oxide spacers extend over the N+ source regions; implanting P-dopant to form P+ body ohmic contact regions between the N+ source regions; and forming a conductive layer over the oxide pads and the oxide spacers for contact with the P+ body ohmic contact regions.