US5566110A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrically erasable programmable read only memory and method of operation
Assignee: Texas Instruments Inc
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Filing: 1995-03-21
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Granted: 1996-10-15
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Expires: 2015-03-21
Abstract
Abstract An improved electrically erasable read only memory (EEPROM) includes a EEPROM cell and a static random access memory (SRAM) cell. Complementary pairs of complementary metal oxide semiconductor (CMOS) transistors connect the gates of transistors forming the EEPROM cell to either the corresponding data nodes of the SRAM cell or to a fixed read or nonzero test voltage. When formed into an array, it is not necessary to replicate differential sense circuitry in every cell. EEPROM transistor pairs are combined into columns which share a common sense latch. The nonsero test voltage allows for measurement of the actual threshold voltages (V T ) of each EEPROM device individually.
Inventors
- 👤 Eric G. Soenen
- 👤 Loulis J. Izzi
- 👤 Thomas F. Adkins
- 👤 Roman Staszewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C11/00; G11C11/005; G06; G06F; G06F2201/00; G06F2201/81
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
48 words
An improved electrically erasable programmable read only memory (EEPROM), comprising: a EEPROM transistor pair, each transistor having a programming terminal; a static random access memory (SRAM) coupled to the EEPROM transistor pair; and a threshold voltage (V T ) test measurement line coupled to the EEPROM transistor pair.
Claim 2
Dependent Claim
48 words
An improved electrically erasable programmable read only memory (EEPROM), comprising: a EEPROM transistor pair, each transistor having a programming terminal; a static random access memory (SRAM) coupled to the EEPROM transistor pair; and a threshold voltage (V T ) test measurement line coupled to the EEPROM transistor pair.
Claim 3
Dependent Claim
31 words
The improved EEPROM of claim 1 wherein a first pair of complementary metal oxide semiconductor (CMOS) transistors couples the V T measurement line to the programming terminals of the EEPROM transistors.
Claim 4
Dependent Claim
24 words
The improved EEPROM of claim 2 wherein a second pair of CMOS transistors couples the SRAM to the programming terminals of the EEPROM transistors.
Claim 5
Dependent Claim
180 words
A differential non-volatile EEPROM memory cell comprising: two column lines; a static latch having two back-to-back logic inverters, using a programming voltage as their supply voltage, connected to the two column lines through two first transmission gates for writing and/or reading of the latch; two EEPROM devices, each having a source and a drain connection, a floating gate, a programming terminal capacitively coupled to the floating gate through a comparatively large tunnel capacitor and a programming terminal capacitively coupled to the floating gate through a comparatively small tunnel capacitor, the EEPROM devices being connected so that their programming terminals with comparatively large tunnel capacitor and programming terminals with comparatively small tunnel capacitors are cross-coupled; two second transmission gates connecting the outputs of the two back-to-back inverters to the two cross-coupled programming terminals of the EEPROM devices, these transmission gates being on when the cell is to be programmed; and two third transmission gates connecting the two cross-coupled programming terminals of the EEPROM devices to a single test voltage, these transmission gates being on when the cell is to be read.
Claim 6
Dependent Claim
180 words
A differential non-volatile EEPROM memory cell comprising: two column lines; a static latch having two back-to-back logic inverters, using a programming voltage as their supply voltage, connected to the two column lines through two first transmission gates for writing and/or reading of the latch; two EEPROM devices, each having a source and a drain connection, a floating gate, a programming terminal capacitively coupled to the floating gate through a comparatively large tunnel capacitor and a programming terminal capacitively coupled to the floating gate through a comparatively small tunnel capacitor, the EEPROM devices being connected so that their programming terminals with comparatively large tunnel capacitor and programming terminals with comparatively small tunnel capacitors are cross-coupled; two second transmission gates connecting the outputs of the two back-to-back inverters to the two cross-coupled programming terminals of the EEPROM devices, these transmission gates being on when the cell is to be programmed; and two third transmission gates connecting the two cross-coupled programming terminals of the EEPROM devices to a single test voltage, these transmission gates being on when the cell is to be read.
Claim 7
Dependent Claim
41 words
The differential non-volatile EEPROM memory cell of claim 4, wherein the drains of the two EEPROM devices are connected to the column lines through two fourth transmission gates, these fourth transmission gates being on when the cell is to be read.
Claim 8
Dependent Claim
189 words
A differential non-volatile EEPROM memory cell comprising two column lines a static latch with differential outputs, using a programming voltage as its supply voltage; two EEPROM devices, each having a source and a drain connection, a floating gate, a programming terminal capacitively coupled to the floating gate through a comparatively large tunnel capacitor and a programming terminal capacitively coupled to the floating gate through a comparatively small tunnel capacitor, these EEPROM devices being connected so that their programming terminals with comparatively large tunnel capacitor and programming terminals with comparatively small tunnel capacitors are cross-coupled; two first transmission gates connecting the outputs of the static latch to the two cross-coupled programming terminals of the EEPROM devices, these transmission gates being on when the cell is to be programmed; two second transmission gates connecting the two cross-coupled programming terminals of the EEPROM devices to a single test voltage, these transmission gates being on when the cell is to be read; and a sense amplifier connected to the two column lines to determine a logic state of the memory cell based on the comparative current sinking capability of the two EEPROM devices.
Claim 9
Dependent Claim
189 words
A differential non-volatile EEPROM memory cell comprising two column lines a static latch with differential outputs, using a programming voltage as its supply voltage; two EEPROM devices, each having a source and a drain connection, a floating gate, a programming terminal capacitively coupled to the floating gate through a comparatively large tunnel capacitor and a programming terminal capacitively coupled to the floating gate through a comparatively small tunnel capacitor, these EEPROM devices being connected so that their programming terminals with comparatively large tunnel capacitor and programming terminals with comparatively small tunnel capacitors are cross-coupled; two first transmission gates connecting the outputs of the static latch to the two cross-coupled programming terminals of the EEPROM devices, these transmission gates being on when the cell is to be programmed; two second transmission gates connecting the two cross-coupled programming terminals of the EEPROM devices to a single test voltage, these transmission gates being on when the cell is to be read; and a sense amplifier connected to the two column lines to determine a logic state of the memory cell based on the comparative current sinking capability of the two EEPROM devices.
Claim 10
Dependent Claim
39 words
The differential non-volatile EEPROM memory cell of claim 6, wherein the drains of the two EEPROM devices are connected to lines common with other such memory cells, these transmission gates being on when the cell is to be tested.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-15 | 2000-04-15 | 2000-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-15 | 2004-04-15 | 2004-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-15 | 2008-04-15 | 2008-10-15 | $7700.00 | Window Closed / Lapsed |