Non-volatile memory cell

Claim 2

A nonvolatile memory cell comprising: a bistable memory cell having at least one input/output node; means coupled to said bistable cell for causing said bistable cell to assume a predetermined one of its stable states when power is applied to said cell; an electrically programmable and electrically erasable (E 2 ) memory cell having two terminals, one of said terminals being coupled to said input/output node of said bistable cell; and, a control line for controlling the clearing of said E 2 cell and the recalling of information from said E 2 cell, said line being coupled to the other terminal of said E 2 cell; whereby a memory cell is realized which has the capability to store information in the absence of power.

Claim 3

The nonvolatile memory cell defined by claim 1 wherein said bistable cell includes a pair of load devices and wherein said means for causing said bistable cell to assume a predetermined one of its stable states comprises an imbalance between said load devices.

Claim 4

The nonvolatile memory cell defined by claim 2 wherein said pair of load devices comprise a pair of depletion mode devices, one of which is larger than the other.

Claim 5

The nonvolatile memory cell defined by claim 1 wherein said E 2 memory cell comprises a floating gate device having a thin oxide region for transporting charge to and from the floating gate.

Claim 6

The nonvolatile memory cell defined by claim 1 wherein a transistor is coupled between said one terminal of said E 2 memory cell and said node of said bistable cell.

Claim 7

A nonvolatile memory cell comprising: a bistable memory cell having at least one input/output node; means coupled to said bistable cell for causing said bistable cell to assume a predetermined one of its stable states when power is applied to said cell; an electrically programmable and electrically erasable (E 2 ) memory cell including two terminals, a floating gate and a thin oxide region through which charge is tunnelled to and from said floating gate, one of said terminals being coupled to said input/output node of said bistable cell; and, a control line for controlling and clearing of said E 2 cell and the recalling of information from said E 2 cell, said line being coupled to the other terminal of said E 2 cell; whereby a memory cell is realized which has the capability to store information in the absence of power.

Claim 8

A nonvolatile memory cell comprising: a bistable memory cell having at least one input/output node; means coupled to said bistable cell for causing said bistable cell to assume a predetermined one of its stable states when power is applied to said cell; an electrically programmable and electrically erasable (E 2 ) memory cell including two terminals, a floating gate and a thin oxide region through which charge is tunnelled to and from said floating gate, one of said terminals being coupled to said input/output node of said bistable cell; and, a control line for controlling and clearing of said E 2 cell and the recalling of information from said E 2 cell, said line being coupled to the other terminal of said E 2 cell; whereby a memory cell is realized which has the capability to store information in the absence of power.

Claim 9

The nonvolatile memory cell defined by claim 6 wherein said bistable cell includes a pair of load devices and wherein said means for causing said bistable cell to assume a predetermined one of its stable states comprises an imbalance between said load devices.

Claim 10

The nonvolatile memory cell defined by claim 7 wherein said pair of load devices comprise a pair of depletion load devices, one of which is larger than the other.

Claim 11

The nonvolatile memory cell defined by claim 8 wherein a transistor is coupled between said one terminal of said E 2 memory cell and said node of said bistable cell.

Claim 12

A nonvolatile memory cell comprising: a bistable memory cell having at least one input/output node and a pair of load devices, one of which is more conductive than the other; an electrically programmable and electrically erasable (E 2 ) memory cell having two terminals, one of said terminals being coupled to said input/output node of said bistable cell; and, a control line for controlling the clearing of said E 2 cell and the recalling of information from said E 2 cell, said line being coupled to the other terminal of said E 2 cell; whereby a memory cell is realized which has the capability to store information in the absence of power.

Claim 13

A nonvolatile memory cell comprising: a bistable memory cell having at least one input/output node and a pair of load devices, one of which is more conductive than the other; an electrically programmable and electrically erasable (E 2 ) memory cell having two terminals, one of said terminals being coupled to said input/output node of said bistable cell; and, a control line for controlling the clearing of said E 2 cell and the recalling of information from said E 2 cell, said line being coupled to the other terminal of said E 2 cell; whereby a memory cell is realized which has the capability to store information in the absence of power.

Claim 14

The nonvolatile memory cell defined by claim 10 wherein said pair of load devices comprise a pair of depletion load devices, one of which is larger than the other.

Claim 15

The nonvolatile memory cell defined by claim 11 wherein said E 2 memory cell comprises a floating gate device having a thin oxide region for transporting charge to and from the floating gate.

Claim 16

The nonvolatile memory cell defined by claim 12 wherein a transistor is coupled between said one terminal of said E 2 memory cell and said node of said bistable cell.