System for optimal electronic debugging and verification employing scheduled cutover of alternative logic simulations

Claim 1

A machine-implemented method for scheduling a plurality of circuit design simulators {S} for debugging of a digital electronic circuit design having no more than N bugs that are discoverable in no more than M(N)=M simulated machine cycles of said digital electronic circuit design, where the n th said bug is discoverable in M(n) simulated machine cycles using any one or more of said plurality of circuit design simulators {S}, each two of which form a simulator pair (S i , S i+1 ), each said simulator S i having an availability fraction h i , having a machine cycle time c i , having an average fix delay time D i equal to the mean time between discovery of and the correction of said n th bug for all values of n, and having a debug time for said n th bug equal to the time required to discover and fix said n th bug, wherein i and n are non-zero positive integers, said method comprising the steps of: (a) estimating the number of said machine cycles M(n ci ) required to discover a cutover bug number n ci for which said debug times are most nearly equivalent in both of an i th said pair of simulators (S i , S i+1 ); (b) estimating a predicted discovery time for said cutover bug number n ci corresponding to the time required to complete said machine cycles M(n ci ) for one of said simulators in said i th pair of simulators (S i , S i+1 ); (c) displaying a debugging simulation schedule for said i th pair of simulators (S i , S i+1 ) wherein said predicted discovery time for said cutover bug number n ci corresponds to the scheduled time for cutover of said simulated machine cycles from the first said simulator S i to the second said simulator S i+1 of said i th pair of simulators (S i , S i+1 ); and (d) during simulation of the digital electronic circuit by the first said simulator S i , transitioning said simulation of the digital electronic circuit to the second said simulator S i+1 at said scheduled time for cutover.