Logically disconnectable virtual-to-physical address translation unit and method for such disconnection

Claim 2

In a microprocessor, a method for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a virtual address tag and a control signal, said control signal selectably having an asserted state or a negated state, said method comprising the steps of: providing a content addressable memory having a number of locations, each location storing a virtual address tag, said content addressable memory comprising a precharge circuit and (i) a comparator for comparing said virtual address tag received at said translation unit with said stored virtual address tag, and (ii) a precharge circuit including a precharged signal line, said precharged signal line being charged by said precharge circuit prior to said comparison and being discharged by said comparator when said virtual address tag received matches said stored virtual address tag; and, upon said translation unit receiving said control signal in said asserted state: (i) remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and (ii) forcing said virtual address tag received to a predetermined value not matching any virtual address tag stored in said content addressable memory.

Claim 3

The method of claim 1 further comprising the step of suppressing a detection of a TLB exception condition.

Claim 4

The method of claim 1 wherein the step of remapping the virtual address further comprises the step of modifying a cacheable memory indicator.

Claim 5

The method of claim 1, further including the step of providing a random access memory having a number of locations, each location of said random access memory corresponding to a location of said content addressable memory, said location of said random access memory storing a physical address, said random access memory including a precharged output bus for outputting said physical address at one of said locations of said random access memory and a circuit responsive to said control signal for prohibiting discharge of said precharged output bus.

Claim 6

A method as in claim 1, wherein said content addressable memory includes a comparator for each location of said content addressable memory.

Claim 7

In a microprocessor a method for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a plurality of input signals and including a plurality of precharged signal lines, each of said precharged signal lines being set to a charged state or a discharged state during an evaluation phase in response to logic states of said plurality of input signals, said method comprising the steps of: remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and forcing said plurality of input signals of said translation unit to predetermined logic states, such that said plurality of precharged signal lines are not discharged during said evaluation phase; wherein said plurality of input signals includes input address lines to a plurality of content addressable memory (CAM) cells and an enable signal for enabling precharge of word lines of said CAM cells, and wherein said plurality of precharged signal lines include a plurality of output bit lines of random access memory (RAM) cells, said plurality of output bit lines of said RAM cells being coupled to a plurality of sense amplifiers, the step of forcing said plurality of input signals of said translation unit to predetermined logic states comprises the steps of: setting said input address lines to predetermined logic states, and deasserting said enable signal so as to prevent said word lines of said CAM cells from being precharged, and disconnecting said plurality of sense-amps from said plurality of output bit lines.

Claim 8

In a microprocessor a method for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a plurality of input signals and including a plurality of precharged signal lines, each of said precharged signal lines being set to a charged state or a discharged state during an evaluation phase in response to logic states of said plurality of input signals, said method comprising the steps of: remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and forcing said plurality of input signals of said translation unit to predetermined logic states, such that said plurality of precharged signal lines are not discharged during said evaluation phase; wherein said plurality of input signals includes input address lines to a plurality of content addressable memory (CAM) cells and an enable signal for enabling precharge of word lines of said CAM cells, and wherein said plurality of precharged signal lines include a plurality of output bit lines of random access memory (RAM) cells, said plurality of output bit lines of said RAM cells being coupled to a plurality of sense amplifiers, the step of forcing said plurality of input signals of said translation unit to predetermined logic states comprises the steps of: setting said input address lines to predetermined logic states, and deasserting said enable signal so as to prevent said word lines of said CAM cells from being precharged, and disconnecting said plurality of sense-amps from said plurality of output bit lines.

Claim 9

The method of claim 6 wherein each of said CAM cells receives as input signals both a selected one of said inputt address lines and a complementary signals of said selected input address line, the step of setting said input address lines comprises the step of forcing both said selected one of said input address line and said complementary signal to a selected logic value.

Claim 10

In a microprocessor, a circuit for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a virtual address tag and a control signal, said control signal having an asserted state or a negated state, said circuit for logically removing a translation unit from operation comprising: a content addressable memory having a number of locations, each location storing a virtual address tag, said content addressable memory comprising a precharge circuit and (i) a comparator for comparing said virtual address tag received with said stored virtual address tag, and (ii) a precharged signal line, said precharged signal line being charged by said precharge circuit prior to said comparison and being discharged by said comparator when said virtual address tag received matches said stored virtual address; a circuit, in response to said control signal, for remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and a circuit for forcing, in response to receiving at said translation unit said asserted state of said control signal, said virtual address tag received to a predetermined value not matching any virtual tag stored in said content addressable memory.

Claim 11

In a microprocessor, a circuit for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a virtual address tag and a control signal, said control signal having an asserted state or a negated state, said circuit for logically removing a translation unit from operation comprising: a content addressable memory having a number of locations, each location storing a virtual address tag, said content addressable memory comprising a precharge circuit and (i) a comparator for comparing said virtual address tag received with said stored virtual address tag, and (ii) a precharged signal line, said precharged signal line being charged by said precharge circuit prior to said comparison and being discharged by said comparator when said virtual address tag received matches said stored virtual address; a circuit, in response to said control signal, for remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and a circuit for forcing, in response to receiving at said translation unit said asserted state of said control signal, said virtual address tag received to a predetermined value not matching any virtual tag stored in said content addressable memory.

Claim 12

The circuit of claim 8 further comprising means for suppressing detection of TTLB exception condition.

Claim 13

The circuit of claim 8, further comprising means for modifying a cacheable memory indicator.

Claim 14

The circuit of claim 8, further including a random access memory having a number of locations, each location of said random access memory corresponding to a location of said content addressable memory, said location of said random access memory storing a physical address, said random access memory comprises: a precharged output bus for output said physical address at one of said locations of said random access memory; and a disabling circuit, said disabling circuit prohibiting discharge of said precharged output bus in response to said control signal.

Claim 15

A method as in claim 8, wherein said content addressable memory includes a comparator for each location of said content addressable memory.

Claim 16

In a microprocessor, a circuit for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a plurality of input signals and including a plurality of precharged signal lines, each of said precharged signal line being set to a charged state or a discharged state during an evaluation phase in response to logic states of said plurality of input signals, said circuit for logically removing a translation unit from operation comprising: a circuit for remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and a circuit for forcing said plurality of input signals of said translation unit to predetermined states, such that said plurality of precharged signal lines of said translation unit are not discharged during said evaluation phase; wherein said plurality of input signals includes input address lines to a plurality of content addressable memory (CAM) cells and an enable signal for enabling precharge of word lines of said CAM cells, and wherein said plurality of precharged signal lines include a plurality of output bit lines of random access memory (RAM) cells, said plurality of output bit lines of said RAM cells being coupled to a plurality of sense amplifiers, said circuit for forcing said plurality of input signals of said translation unit to predetermined logic states further comprising: a circuit for setting said input address lines to predetermined logic states; a circuit for deasserting said enable signal so as to prevent said word lines of said CAM cells from being precharged, and a circuit for disconnecting said plurality of sense-amps from said plurality of output bit lines of said RAM cells.

Claim 17

In a microprocessor, a circuit for logically removing a translation unit from operation, said translation unit being provided for translating virtual addresses to physical addresses, said translation unit receiving a plurality of input signals and including a plurality of precharged signal lines, each of said precharged signal line being set to a charged state or a discharged state during an evaluation phase in response to logic states of said plurality of input signals, said circuit for logically removing a translation unit from operation comprising: a circuit for remapping the virtual address space to operate under a fixed virtual address to physical address mapping scheme; and a circuit for forcing said plurality of input signals of said translation unit to predetermined states, such that said plurality of precharged signal lines of said translation unit are not discharged during said evaluation phase; wherein said plurality of input signals includes input address lines to a plurality of content addressable memory (CAM) cells and an enable signal for enabling precharge of word lines of said CAM cells, and wherein said plurality of precharged signal lines include a plurality of output bit lines of random access memory (RAM) cells, said plurality of output bit lines of said RAM cells being coupled to a plurality of sense amplifiers, said circuit for forcing said plurality of input signals of said translation unit to predetermined logic states further comprising: a circuit for setting said input address lines to predetermined logic states; a circuit for deasserting said enable signal so as to prevent said word lines of said CAM cells from being precharged, and a circuit for disconnecting said plurality of sense-amps from said plurality of output bit lines of said RAM cells.

Claim 18

A circuit for logically removing a translation unit from operation, as in claim 13, wherein each of said CAM cells receives as input signals both a selected one of said input address lines and a complementary signal of said selected input address line, said circuit for setting said input address lines further comprising a circuit for forcing both said selected input address line and said complementary signal to a selected logic value.