Patent US5564030A successfully refreshed from Google Patents.
US5564030A
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Circuit and method for detecting segment limit errors for code fetches
Assignee: TU WEICHI
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Filing: 1994-02-08
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Granted: 1996-10-08
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Expires: 2014-02-08
Abstract
Abstract A segment limit check circuit performs limit checks on fetch addresses generated by a CPU. The circuit and method for performing the fetch limit check are simplified over the prior art by effectively moving the fetch limit check to linear address space. For a microprocessor that uses physical addresses of 32-bits and performs fetches as 16-byte aligned accesses, the circuit of the present invention generates a 33-bit linear address and a 33-bit upper limit value. A comparator compares the upper 29 bits of the linear address with the upper 29-bits of the upper limit value. If a match occurs, the circuit decodes the 4 low-order bits of the upper limit value to determine which of the 16 instruction bytes (if any) fall outside the segment limit.
Inventors
- 👤 Graham B. Whitted, III
- 👤 Hsiao-Shih Chang
- 👤 James A. Kane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441; G06F9/30003; G06F9/30007; G06F9/30021; G06F9/38; G06F9/3802
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
240 words
A method of performing a segment limit check for a fetch request generated by a central processing unit (CPU) of a microprocessor, said microprocessor performing fetches as 16-byte aligned accesses, said method comprising the steps of: receiving a 32-bit effective address from said CPU; adding said 32-bit effective address to a 32-bit segment base address to produce a 33-bit linear address; adding said 32-bit segment base address to a 32-bit segment limit address to produce a 33-bit upper limit, said 32-bit segment limit address being an effective address that specifies a segment limit in a physical memory; and comparing a first 29-bit value to a second 29-bit value, said first 29-bit value comprising the high-order 29 bits of said 33-bit linear address and said second 29-bit value comprising the high-order 29 bits of said 33-bit limit address, and performing one of: indicating that all 16 byte locations of said fetch request exceed said segment limit in said physical memory when said first 29-bit value exceeds said second 29-bit value; indicating that none of the 16 byte locations of said fetch request exceeds said segment limit in said physical memory when said first 29-bit value is less than said second 29-bit value; or decoding the 4 low-order bits of said 33-bit upper limit when said first 29-bit value is equal to said second 29-bit value to determine which of the 16 byte locations exceed said segment limit in said physical memory.
Claim 2
Independent Claim
240 words
A method of performing a segment limit check for a fetch request generated by a central processing unit (CPU) of a microprocessor, said microprocessor performing fetches as 16-byte aligned accesses, said method comprising the steps of: receiving a 32-bit effective address from said CPU; adding said 32-bit effective address to a 32-bit segment base address to produce a 33-bit linear address; adding said 32-bit segment base address to a 32-bit segment limit address to produce a 33-bit upper limit, said 32-bit segment limit address being an effective address that specifies a segment limit in a physical memory; and comparing a first 29-bit value to a second 29-bit value, said first 29-bit value comprising the high-order 29 bits of said 33-bit linear address and said second 29-bit value comprising the high-order 29 bits of said 33-bit limit address, and performing one of: indicating that all 16 byte locations of said fetch request exceed said segment limit in said physical memory when said first 29-bit value exceeds said second 29-bit value; indicating that none of the 16 byte locations of said fetch request exceeds said segment limit in said physical memory when said first 29-bit value is less than said second 29-bit value; or decoding the 4 low-order bits of said 33-bit upper limit when said first 29-bit value is equal to said second 29-bit value to determine which of the 16 byte locations exceed said segment limit in said physical memory.
Claim 3
Dependent Claim
263 words
A fetch limit check circuit for a microprocessor, said microprocessor having a central processing unit (CPU) that generates a fetch request and a corresponding effective address for performing an N-byte aligned fetch from a physical memory, said microprocessor also having a first register that specifies a segment base address and having a second register that specifies a segment limit address, said limit check circuit comprising: a first adder that adds said effective address to said segment base address to generate a linear address; a second adder that adds said limit address to said segment base address to generate an upper limit; a comparator that compares a first value to a second value, said first value formed from all but the X low-order bits of said linear address and said second value formed from all but the X low-order bits of said limit address, wherein 2 x =N and N is greater than or equal to 4, and wherein said linear address and said upper limit each comprise greater than X bits; and decode logic that receives the X low-order bits of said upper limit, and when said first value and said second value are equal determines from said X low-order bits which of N instruction bytes for said fetch request exceed a segment limit in said physical memory, wherein said first adder generates a first carry bit, said first carry bit forming a most significant bit of said linear address, and wherein said second adder generates a second carry bit, said second carry bit forming a most significant bit of said upper limit.
Claim 4
Dependent Claim
263 words
A fetch limit check circuit for a microprocessor, said microprocessor having a central processing unit (CPU) that generates a fetch request and a corresponding effective address for performing an N-byte aligned fetch from a physical memory, said microprocessor also having a first register that specifies a segment base address and having a second register that specifies a segment limit address, said limit check circuit comprising: a first adder that adds said effective address to said segment base address to generate a linear address; a second adder that adds said limit address to said segment base address to generate an upper limit; a comparator that compares a first value to a second value, said first value formed from all but the X low-order bits of said linear address and said second value formed from all but the X low-order bits of said limit address, wherein 2 x =N and N is greater than or equal to 4, and wherein said linear address and said upper limit each comprise greater than X bits; and decode logic that receives the X low-order bits of said upper limit, and when said first value and said second value are equal determines from said X low-order bits which of N instruction bytes for said fetch request exceed a segment limit in said physical memory, wherein said first adder generates a first carry bit, said first carry bit forming a most significant bit of said linear address, and wherein said second adder generates a second carry bit, said second carry bit forming a most significant bit of said upper limit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |