Patent US5561772A successfully refreshed from Google Patents.
US5561772A
Expired / Lapsed
US
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Expansion bus system for replicating an internal bus as an external bus with logical interrupts replacing physical interrupt lines
Assignee: PDACO Ltd
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Filing: 1994-07-26
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Granted: 1996-10-01
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Expires: 2014-07-26
Abstract
Abstract A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.
Inventors
- 👤 Pascal Dornier
- 👤 Dan Kikinis
- 👤 William J. Seiler
- 👤 William S. Jacobs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:43
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; G06K; G06K15/00; H; H04; H04N; H04N1/00; H04N1/00127; H04N1/04; H04N1/0461; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; H04M; H04M1/00; H04M1/72; H04M1/725; H04M3/00; H04M3/42; H04M3/42314; H04M3/42323; H04N1/00204; H04N1/00278; H04N1/113; H04N1/1135; H04N1/12; H04N2201/00; H04N2201/0008; H04N2201/001; H04N2201/0074; H04N2201/0077; H04N2201/0081; H04N2201/0082; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
163 words
A computer bus expansion system comprising: an internal bus having data, address, and control lines, but no interrupt lines; bus control circuitry coupled to the internal bus and to a central processing unit (CPU); a first translator connected to the internal bus; an intermediate bus of lesser width than the internal bus, and connected to the first translator; a second translator connected to the intermediate bus; and an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; wherein interrupts are addresses unique to specific peripheral devices, the addresses are translated from address lines of the expansion bus through the second translator to the intermediate bus, and through the first translator from the intermediate bus onto address lines of the internal bus, the translations transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.
Claim 2
Dependent Claim
163 words
A computer bus expansion system comprising: an internal bus having data, address, and control lines, but no interrupt lines; bus control circuitry coupled to the internal bus and to a central processing unit (CPU); a first translator connected to the internal bus; an intermediate bus of lesser width than the internal bus, and connected to the first translator; a second translator connected to the intermediate bus; and an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; wherein interrupts are addresses unique to specific peripheral devices, the addresses are translated from address lines of the expansion bus through the second translator to the intermediate bus, and through the first translator from the intermediate bus onto address lines of the internal bus, the translations transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.
Claim 3
Dependent Claim
42 words
A computer bus expansion system as in claim 1 further comprising a peripheral device connected to the expansion bus, the peripheral device adapted for issuing an interrupt as an address specific to the peripheral device on address lines of the expansion bus.
Claim 4
Dependent Claim
49 words
A computer bus expansion system as in claim 1 wherein the intermediate bus is a Centronics™-type cable with 25-pin end connectors, and the first translator is adapted for operating as in industry-standard parallel port as well as adapted for operating as a bus translator transparent to system operating code.
Claim 5
Dependent Claim
29 words
A computer bus expansion system as in claim 1 wherein the internal and external buses are compressed buses wherein 32-bit addresses and 32-bit data are multiplexed on 32 lines.
Claim 6
Dependent Claim
186 words
A computer system comprising: an internal bus having data, address, and control lines, but no interrupt lines; bus control circuitry coupled to the internal bus and to a central processing unit (CPU); system memory; first peripheral ports connected to the internal bus and adapted for connecting peripheral devices; a first translator connected to the internal bus; an intermediate bus of lesser width than the internal bus, and connected to the first translator; a second translator connected to the intermediate bus; an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; and second peripheral ports connected to the expansion bus and adapted for connecting peripheral devices; wherein interrupts are addresses unique to specific peripheral devices connected to the peripheral ports, and wherein addresses, data, and control signals are translated between the internal bus and the expansion bus through the first and second translators and the intermediate bus transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.
Claim 7
Dependent Claim
186 words
A computer system comprising: an internal bus having data, address, and control lines, but no interrupt lines; bus control circuitry coupled to the internal bus and to a central processing unit (CPU); system memory; first peripheral ports connected to the internal bus and adapted for connecting peripheral devices; a first translator connected to the internal bus; an intermediate bus of lesser width than the internal bus, and connected to the first translator; a second translator connected to the intermediate bus; an expansion bus having the same number of lines as and equivalent signals to the internal bus, the expansion bus connected to the second translator; and second peripheral ports connected to the expansion bus and adapted for connecting peripheral devices; wherein interrupts are addresses unique to specific peripheral devices connected to the peripheral ports, and wherein addresses, data, and control signals are translated between the internal bus and the expansion bus through the first and second translators and the intermediate bus transparent to system operating code, and wherein the bus control circuitry decodes the addresses to the CPU as interrupts specific to the associated peripheral devices.
Claim 8
Dependent Claim
42 words
A computer system as in claim 5 further comprising peripheral devices connected to the internal bus and the expansion bus at peripheral ports, the peripheral devices adapted for issuing interrupts as addresses specific to the peripheral devices connected to the peripheral ports.
Claim 9
Dependent Claim
47 words
A computer system as in claim 5 wherein the intermediate bus is a Centronics™-type cable with 25-pin end connectors, and the first translator is adapted for operating as in industry-standard parallel port as well as adapted for operating as a bus translator transparent to system operating code.
Claim 10
Dependent Claim
27 words
A computer system as in claim 5 wherein the internal and external buses are compressed buses wherein 32-bit addresses and 32-bit data are multiplexed on 32 lines.
Claim 11
Independent Claim
144 words
A method for issuing an interrupt from a peripheral device coupled to a first bus external to a computer to a central processing unit (CPU) coupled to a second bus internal to the computer, wherein the first and second buses have the same number of lines and equivalent signals and each lack interrupt lines, the method comprising steps of: (a) issuing an address on address lines of the first bus by the peripheral device, the address unique to the peripheral device; (b) translating the address through a first translating circuit onto an intermediate bus of less width than the first and second buses; (c) translating the address through a second translating circuit from the intermediate bus onto address lines of the second bus; and (d) decoding the address as an interrupt specific to the peripheral device at control circuitry coupled to the second bus.
Claim 12
Independent Claim
144 words
A method for issuing an interrupt from a peripheral device coupled to a first bus external to a computer to a central processing unit (CPU) coupled to a second bus internal to the computer, wherein the first and second buses have the same number of lines and equivalent signals and each lack interrupt lines, the method comprising steps of: (a) issuing an address on address lines of the first bus by the peripheral device, the address unique to the peripheral device; (b) translating the address through a first translating circuit onto an intermediate bus of less width than the first and second buses; (c) translating the address through a second translating circuit from the intermediate bus onto address lines of the second bus; and (d) decoding the address as an interrupt specific to the peripheral device at control circuitry coupled to the second bus.
Claim 13
Dependent Claim
40 words
The method of claim 9 wherein peripheral devices are connected to the internal bus and the expansion bus at peripheral ports, the peripheral devices adapted for issuing interrupts as addresses specific to the peripheral devices connected to the peripheral ports.
Claim 14
Dependent Claim
45 words
The method of claim 9 wherein the intermediate bus is a Centronics™-type cable with 25-pin end connectors, and the first translator is adapted for operating as in industry-standard parallel port as well as adapted for operating as a bus translator transparent to system operating code.
Claim 15
Dependent Claim
25 words
The method of claim 9 wherein the internal and external buses are compressed buses wherein 32-bit addresses and 32-bit data are multiplexed on 32 lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |