Patent US6462646B2 successfully refreshed from Google Patents.
US5561384A
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US
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Input/output driver circuit for isolating with minimal power consumption a peripheral component from a core section
Assignee: Advanced Micro Devices Inc
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Filing: 1995-11-08
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Granted: 1996-10-01
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Expires: 2015-11-08
Abstract
Abstract Within an integrated circuit, an input/output driver circuit is provided. The input/output driver circuit is configured to provide electrical isolation and power savings when the integrated circuit is configured into a computer system such as a personal information device. By providing a mechanism permitting removal of power from the driver circuit, the integrated circuit inhibits current flow from the integrated circuit into a powered-down peripheral device. A force term is activated, when electrical isolation is desired, to inhibit current flow into or from the integrated circuit via an input/output pad voltage level. A power savings is enabled by allowing the power down of peripheral devices coupled to the integrated circuit without the need for external buffer circuits.
Inventors
- 👤 Daniel B. Reents
- 👤 Michael S. Quimby
- 👤 Carl K. Wakeland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
74 words
An integrated circuit comprising: an input/output driver circuit interposed between a core section and an input/output pad upon a single monolithic circuit, wherein said input/output driver circuit includes: a pull-up transistor connected between a first power source and said input/output pad; a pull-down transistor connected between a ground and said input/output pad; and a force term signal input into a gate of said pull-down transistor during times in which a partial reset is detected.
Claim 2
Dependent Claim
74 words
An integrated circuit comprising: an input/output driver circuit interposed between a core section and an input/output pad upon a single monolithic circuit, wherein said input/output driver circuit includes: a pull-up transistor connected between a first power source and said input/output pad; a pull-down transistor connected between a ground and said input/output pad; and a force term signal input into a gate of said pull-down transistor during times in which a partial reset is detected.
Claim 3
Dependent Claim
24 words
The integrated circuit as recited in claim 1, wherein said pull-up transistor is turned off during times in which said partial reset is detected.
Claim 4
Dependent Claim
25 words
The integrated circuit as recited in claim 1, wherein said pull-up transistor is turned on during times in which said partial reset is not detected.
Claim 5
Dependent Claim
83 words
The integrated circuit as recited in claim 1, wherein said input/output driver circuit further comprising: a driving-high transistor connected between said first power source and said input/output pad; a driving-low transistor connected between said ground and said input/output pad; and a pair of level translator/predriver circuits connected to respective gate terminals of said driving-high and driving low-transistors, wherein one of said level translator/predriver circuits coupled is to receive an output signal from said core section and to activate said driving-high transistor coupled thereto.
Claim 6
Dependent Claim
24 words
The integrated circuit as recited in claim 4, wherein activated said driving-high transistor causes coupling of said first power source to said input/output pad.
Claim 7
Dependent Claim
22 words
The integrated circuit as recited in claim 4, wherein activated said driving-low transistor causes coupling of said ground to said input/output pad.
Claim 8
Dependent Claim
26 words
The integrated circuit as recited in claim 1, wherein said input/output pad is electrically coupled to a lead extending from a package surrounding said integrated circuit.
Claim 9
Dependent Claim
36 words
The integrated circuit as recited in claim 1, further comprising a plurality of input/output driver circuits within an input/output section, each input/output driver circuit is coupled between a portion of said core and an input/output pad.
Claim 10
Dependent Claim
95 words
An input/output driver circuit coupled between a core section and an input/output pad, said input/output driver circuit comprising: selectively operable pull-up and pull-down transistors connected in series between a first power source and a ground; selectively operable driving-high transistor and driving-low transistors connected in series between said ground and both said first power source as well as a clamped second power source; and a mechanism for permitting deactivation of said first and second power sources and for activating said pull-down transistor at substantially the same time as said first and second power sources are deactivated.
Claim 11
Dependent Claim
95 words
An input/output driver circuit coupled between a core section and an input/output pad, said input/output driver circuit comprising: selectively operable pull-up and pull-down transistors connected in series between a first power source and a ground; selectively operable driving-high transistor and driving-low transistors connected in series between said ground and both said first power source as well as a clamped second power source; and a mechanism for permitting deactivation of said first and second power sources and for activating said pull-down transistor at substantially the same time as said first and second power sources are deactivated.
Claim 12
Dependent Claim
41 words
The input/output driver circuit as recited in claim 9, wherein said input/output pad is connected within the series path between said pull-up and pull-down transistors and is further connected within the series path between said driving-high transistor and said driving-low transistor.
Claim 13
Dependent Claim
30 words
The input/output driver circuit as recited in claim 9, further comprising a translator/predriver circuit connected between said core section and a gate terminal of each said driving-low and driving-high transistors.
Claim 14
Dependent Claim
53 words
The input/output driver circuit as recited in claim 9, wherein said clamped second power source comprises: a first diode arranged between a source terminal of said driving-high transistor and said second clamped power source; and a second diode arranged between a drain terminal of said driving-high transistor and said second clamped power source.
Claim 15
Dependent Claim
43 words
The input/output driver circuit as recited in claim 9, wherein said mechanism comprises a switch within a power supply which provides said first and second power sources, said switch is adapted for disconnecting said first and second power sources from said driving-high transistor.
Claim 16
Dependent Claim
39 words
The input/output driver circuit as recited in claim 9, wherein said mechanism comprises a circuit within said core which produces a force term signal responsive to user input upon a pair of input pins configured upon said integrated circuit.
Claim 17
Dependent Claim
24 words
The input/output driver circuit as recited in claim 14, wherein said force term signal is coupled onto a gate terminal of said pull-down transistor.
References Cited (Backward Citations)
US5450027A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |