Low-power-dissipation CMOS circuits

Claim 2

A CMOS circuit comprising a p-channel transistor having source, drain and gate electrodes, an n-channel transistor having source, drain and gate electrodes, first means connecting said gate electrodes together, second means connecting said drain electrodes together, an input terminal directly connected to said first connecting means, means for applying to said input terminal an input waveform representative of binary data signals, an output terminal connected to said second connecting means, and means connecting at least one of said source electrodes to a pulsed power supply having a waveform that is in phase with said input waveform.

Claim 3

A CMOS circuit comprising a p-channel transistor having source, drain and gate electrodes, an n-channel transistor having source, drain and gate electrodes, first means connecting said gate electrodes together, second means connecting said drain electrodes together, an input terminal connected to said first connecting means, an output terminal connected to said second connecting means, means connecting at least one of said source electrodes to a pulsed power supply, means for applying input data signals to said input terminal, a constant-value power supply, and means responsive to data signals being actively supplied by said input data applying means for connecting at least one of the source electrodes to the pulsed power supply and responsive to data not being actively applied by said input data applying means for connecting said at least one of the source electrodes to the constant-value power supply.

Claim 4

A CMOS circuit comprising a p-channel transistor having source, drain and gate electrodes, an n-channel transistor having source, drain and gate electrodes, first means connecting said gate electrodes together, second means connecting said drain electrodes together, an input terminal connected to said first connecting means, an output terminal connected to said second connecting means, means connecting at least one of said source electrodes to a pulsed power supply, means for applying input data signals to said input terminal, a constant-value power supply, and means responsive to data signals being actively supplied by said input data applying means for connecting at least one of the source electrodes to the pulsed power supply and responsive to data not being actively applied by said input data applying means for connecting said at least one of the source electrodes to the constant-value power supply.

Claim 5

A circuit as in claim 1 wherein one of said source electrodes is connected to a pulsed power supply and the other one of said source electrodes is connected to a point of reference potential.

Claim 6

A circuit as in claim 3 wherein said pulsed power supply provides a repetitive four-phase waveform characterized by POWER-UP, VALID, POWER-DOWN and DEAD phases, wherein said VALID and DEAD phases are characterized by voltage levels that are respectively representative of binary signals in the circuit, and said POWER-UP and POWER-DOWN phases are characterized by ramped voltage transitions between said DEAD and VALID phases.

Claim 7

A circuit as in claim 4 further including an additional n-channel transistor having source, drain and gate electrodes, means connecting the source-to-drain path of said additional transistor in series between the source electrode of said first-mentioned n-channel transistor and said point of reference potential, an additional p-channel transistor having source, drain and gate electrodes, means connecting the source-to-drain path of said additional p-channel transistor in parallel with the source-to-drain path of said first-mentioned p-channel transistor, third means connecting the gate electrodes of said additional transistors together, and an additional input terminal connected to said third connecting means, whereby signals appearing at said output terminal are representative of the NAND logic function of signals applied to said input terminals.

Claim 8

A circuit as in claim 4 further including an additional p-channel transistor having source, drain and gate electrodes, means connecting the source-to-drain path of said additional transistor in series between the drain electrodes of said first-mentioned p-channel transistor and said n-channel transistor such that said output terminal remains connected to the drain electrode of said n-channel transistor, an additional n-channel transistor having source, drain and gate electrodes, means connecting the source-to-drain path of said additional n-channel transistor in parallel with the source-to-drain path of said first-mentioned n-channel transistor, and an additional input terminal connected to said third connecting means, whereby signals appearing at said output terminal are representative of the NOR logic function of signals applied to said input terminals.

Claim 9

A circuit as in claim 4 further including an additional p-channel transistor and an additional n-channel transistor each having source, drain and gate electrodes, means connecting the source-to-drain path of said additional p-channel transistor in series between the drain of said first-mentioned p-channel transistor and said output terminal, means connecting the source-to-drain path of said additional n-channel transistor in series between the drain of said first-mentioned n-channel transistor and said output terminal, a direct electrical connection extending between the drains of said first-mentioned p- and n-channel transistors, and additional input terminals respectively connected to the gate electrodes of said additional transistors, whereby complementary binary signals respectively applied to said additional input terminals are determinative of whether or not signals applied to said first-mentioned input terminal are gated to said output terminal.

Claim 10

A circuit as in claim 4 further including an additional p-channel transistor having source, drain and gate electrodes, an additional n-channel transistor having source, drain and gate electrodes, third means connecting the gate electrodes of said additional transistors together, fourth means connecting the drain electrodes of said additional transistors together, an additional output terminal connected to said fourth connecting means, fifth means connecting said additional output terminal to said input terminal, sixth means connecting said third connecting means to said first-mentioned output terminal, and means connecting at least one of the source electrodes of said additional transistors to said pulsed power supply, whereby complementary binary signals respectively appear at said output terminals indicative of whether or not said circuit is storing a "0" or a "1" representation.