US5559987A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-06-30
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Granted: 1996-09-24
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Expires: 2014-06-30
Abstract
Abstract A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.
Inventors
- 👤 Denis Foley
- 👤 Maurice B. Steinman
- 👤 Stephen R. VanDoren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
255 words
In a computer system having at least one processor module coupled to a system bus operating in accordance with a SNOOPING bus protocol, said system bus capable of transmitting system bus commands and addresses, and each of said processor modules including a processor which issues processor commands and addresses, an address interface coupled to said system bus, said address interface including interface pipeline means for receiving and storing said system bus commands and addresses in an ordered sequence, and a Duplicate Tag memory coupled to said address interface, said duplicate Tag memory including means for storing Duplicate Tag addresses and Duplicate Tag status information, a method of updating said Duplicate Tag status information, comprising the steps of: providing by one of said processors to said address interface of said one of said processors, processor commands and addresses for modification of an entry of Duplicate Tag status information of said one of said processors; receiving and storing by said interface pipeline means of said address interface of said one of said processors, system bus command and address information from said system bus; determining if said system bus commands and addresses received and stored in said interface pipeline means are valid; and if said determining step establishes that there are no valid system bus commands and addresses in said interface pipeline means, causing an updating of said Duplicate Tag status information in accordance with said processor commands and addresses for modification without determining if said processor commands and addresses conflict with said system bus commands and addresses.
Claim 2
Dependent Claim
255 words
In a computer system having at least one processor module coupled to a system bus operating in accordance with a SNOOPING bus protocol, said system bus capable of transmitting system bus commands and addresses, and each of said processor modules including a processor which issues processor commands and addresses, an address interface coupled to said system bus, said address interface including interface pipeline means for receiving and storing said system bus commands and addresses in an ordered sequence, and a Duplicate Tag memory coupled to said address interface, said duplicate Tag memory including means for storing Duplicate Tag addresses and Duplicate Tag status information, a method of updating said Duplicate Tag status information, comprising the steps of: providing by one of said processors to said address interface of said one of said processors, processor commands and addresses for modification of an entry of Duplicate Tag status information of said one of said processors; receiving and storing by said interface pipeline means of said address interface of said one of said processors, system bus command and address information from said system bus; determining if said system bus commands and addresses received and stored in said interface pipeline means are valid; and if said determining step establishes that there are no valid system bus commands and addresses in said interface pipeline means, causing an updating of said Duplicate Tag status information in accordance with said processor commands and addresses for modification without determining if said processor commands and addresses conflict with said system bus commands and addresses.
Claim 3
Dependent Claim
100 words
The method of updating said Duplicate Tag status information as set forth in claim 1, further comprising the step of: if said determining step establishes that there are valid system bus commands and addresses in said interface pipeline means, further determining whether said processor commands and addresses for modification conflict with said system bus commands and addresses; and causing an updating of said Duplicate Tag status information in accordance with said processor commands and addresses for modification if said further determining determines that said processor commands and addresses for modification do not conflict with said system bus commands and addresses.
Claim 4
Dependent Claim
42 words
The method of updating said Duplicate Tag status information as set forth in claim 2, wherein the step of further determining includes comparing within said interface pipeline means said processor commands and addresses for modification with said system bus commands and addresses.
Claim 5
Dependent Claim
244 words
In a computer system having at least one processor module coupled to a system bus operating in accordance with a SNOOPING bus protocol, said system bus capable of transmitting system bus commands and addresses, and each of said processor modules including a processor which issues processor commands and addresses, an address interface coupled to said system bus, said address interface including interface pipeline means for receiving and storing said system bus commands and addresses in an ordered sequence, and a Duplicate Tag memory coupled to said address interface, said Duplicate Tag memory including means for storing Duplicate Tag addresses and Duplicate Tag status information, an apparatus for updating said Duplicate Tag status information, comprising: means for providing by one of said processors to said address interface of said one of said processors, processor commands and addresses for modification of an entry of Duplicate Tag status information of said one of said processors; means for determining if said system bus commands and addresses received and stored in said interface pipeline means are valid; and means for causing an updating of said Duplicate Tag status information in accordance with said processor commands and addresses for modification without determining if said processor commands and addresses conflict with said system bus commands and addresses, said means for causing an updating causing said updating in response to a determination by said means for determining that there are no valid system bus commands and addresses in said interface pipeline means.
Claim 6
Dependent Claim
244 words
In a computer system having at least one processor module coupled to a system bus operating in accordance with a SNOOPING bus protocol, said system bus capable of transmitting system bus commands and addresses, and each of said processor modules including a processor which issues processor commands and addresses, an address interface coupled to said system bus, said address interface including interface pipeline means for receiving and storing said system bus commands and addresses in an ordered sequence, and a Duplicate Tag memory coupled to said address interface, said Duplicate Tag memory including means for storing Duplicate Tag addresses and Duplicate Tag status information, an apparatus for updating said Duplicate Tag status information, comprising: means for providing by one of said processors to said address interface of said one of said processors, processor commands and addresses for modification of an entry of Duplicate Tag status information of said one of said processors; means for determining if said system bus commands and addresses received and stored in said interface pipeline means are valid; and means for causing an updating of said Duplicate Tag status information in accordance with said processor commands and addresses for modification without determining if said processor commands and addresses conflict with said system bus commands and addresses, said means for causing an updating causing said updating in response to a determination by said means for determining that there are no valid system bus commands and addresses in said interface pipeline means.
Claim 7
Dependent Claim
119 words
The apparatus for updating said Duplicate Tag status information as set forth in claim 4, further comprising: means for further determining whether said processor commands and addresses for modification conflict with said system bus commands and addresses, if said means for determining establishes that there are valid system bus commands and addresses in said interface pipeline means; and second means for causing an updating of said Duplicate Tag status information in accordance with said processor commands and addresses for modification, said second means for causing an updating causing said updating in response to a determination by said means for further determining that said processor commands and addresses for modification do not conflict with said system bus commands and addresses.
Claim 8
Dependent Claim
38 words
The apparatus for updating said Duplicate Tag status information as set forth in claim 5, wherein said interface pipeline means includes means for comparing said processor commands and addresses for modification with said system bus commands and addresses.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |