Data compression device allowing detection of signals of diverse wave forms

Claim 2

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; and a controller with a control input, a first input, an output, and an address output; with the control input connected to said control output of said analog-to-digital converter, the first input connected to said second outputs of said data processors, the output connected to said second control inputs of said data processors, and the address output connected to said address inputs of said data processors; wherein each data processor comprises: an individual working memory; a comparator with the following elements, inputs, and outputs: a data input and a first input which constitute said data input and said second input of said data processor, a second input, and outputs, wherein said comparator comprises a first adder having first and second inputs constituting said data input and said second input of said comparator, a first output, and a second output constituting one of said outputs of said comparator; a second adder having a first input connected to said first output of said first adder, a second input, and an output constituting one of said outputs of said comparator; and a multiplexer having a first input connected to said second output of said first adder, a second input constituting said first input of said comparator and an output connected to said second input of said second adder; said working memory having a data input, an address input, a first input, a second input, a first output, and a second output; with said first input constituting said data input, said address input, and said first control input of said data processor, said first output constituting said first output of said data processor and connected to said second input of said comparator; a control circuit with the following inputs and outputs: first and second inputs connected to said outputs of said comparator, third and fourth inputs constituting said second control input and said first input of said data processor, a fifth input connected to said second output of said working memory, a sixth input constituting said first control input of said data processor, a first output connected to said second input of said working memory, and an output; and a read only memory having an input connected to said first output of said control circuit and an output constituting said second output of said data processor.

Claim 3

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; and a controller with a control input, a first input, an output, and an address output; with the control input connected to said control output of said analog-to-digital converter, the first input connected to said second outputs of said data processors, the output connected to said second control inputs of said data processors, and the address output connected to said address inputs of said data processors; wherein each data processor comprises: an individual working memory; a comparator with the following elements, inputs, and outputs: a data input and a first input which constitute said data input and said second input of said data processor, a second input, and outputs, wherein said comparator comprises a first adder having first and second inputs constituting said data input and said second input of said comparator, a first output, and a second output constituting one of said outputs of said comparator; a second adder having a first input connected to said first output of said first adder, a second input, and an output constituting one of said outputs of said comparator; and a multiplexer having a first input connected to said second output of said first adder, a second input constituting said first input of said comparator and an output connected to said second input of said second adder; said working memory having a data input, an address input, a first input, a second input, a first output, and a second output; with said first input constituting said data input, said address input, and said first control input of said data processor, said first output constituting said first output of said data processor and connected to said second input of said comparator; a control circuit with the following elements, inputs, and outputs: first and second inputs connected to said outputs of said comparator, third and fourth inputs constituting said second control input and said first input of said data processor, a fifth input connected to said second output of said working memory, a sixth input constituting said first control input of said data processor, a first output connected to said second input of said working memory, wherein said control circuit comprises a first comparator having first and second inputs constituting said first and second inputs of said control circuit, and an output; an OR gate having a first input connected to said output of said first comparator circuit, a second input and an output; a second comparator circuit having first and second inputs constituting said fifth and sixth inputs of said control circuit, and an output connected to said second input of said OR gate; a flip-flop having a first input connected to said output of said OR gate, second and third inputs constituting said fourth and sixth inputs of said control circuit, and first and second outputs; a NOT gate having an input connected to said first output of said flip-flop and an output constituting said first output of said control circuit; and an AND gate having a first input connected to said second output of said flip-flop, a second input constituting said third input of said control circuit, and an output constituting said second output of said control circuit; and a read only memory having an input connected to said first output of said control circuit and an output constituting said second output of said data processor.

Claim 4

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; and a controller with a control input, a first input, an output, and an address output; with the control input connected to said control output of said analog-to-digital converter, the first input connected to said second outputs of said data processors, the output connected to said second control inputs of said data processors, and the address output connected to said address inputs of said data processors; wherein each data processor comprises: an individual working memory; a comparator with the following elements, inputs, and outputs: a data input and a first input which constitute said data input and said second input of said data processor, a second input, and outputs, wherein said comparator comprises a first adder having first and second inputs constituting said data input and said second input of said comparator, a first output, and a second output constituting one of said outputs of said comparator; a second adder having a first input connected to said first output of said first adder, a second input, and an output constituting one of said outputs of said comparator; and a multiplexer having a first input connected to said second output of said first adder, a second input constituting said first input of said comparator and an output connected to said second input of said second adder; said working memory having a data input, an address input, a first input, a second input, a first output, and a second output; with said first input constituting said data input, said address input, and said first control input of said data processor, said first output constituting said first output of said data processor and connected to said second input of said comparator; a control circuit with the following elements, inputs, and outputs: first and second inputs connected to said outputs of said comparator, third and fourth inputs constituting said second control input and said first input of said data processor, a fifth input connected to said second output of said working memory, a sixth input constituting said first control input of said data processor, a first output connected to said second input of said working memory, wherein said control circuit comprises a first comparator having first and second inputs constituting said first and second inputs of said control circuit, and an output; an OR gate having a first input connected to said output of said first comparator circuit, a second input and an output; a second comparator circuit having first and second inputs constituting said fifth and sixth inputs of said control circuit, and an output connected to said second input of said OR gate; a flip-flop having a first input connected to said output of said OR gate, second and third inputs constituting said fourth and sixth inputs of said control circuit, and first and second outputs; a NOT gate having an input connected to said first output of said flip-flop and an output constituting said first output of said control circuit; and an AND gate having a first input connected to said second output of said flip-flop, a second input constituting said third input of said control circuit, and an output constituting said second output of said control circuit; and a read only memory having an input connected to said first output of said control circuit and an output constituting said second output of said data processor.

Claim 5

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; a controller with a control input, a first input, an output, and an address output; with the control input connected to said control output of said analog-to-digital converter, the first input connected to said second outputs of said data processors, the output connected to said second control inputs of said data processors, and the address output connected to said address inputs of said data processors; and, a signal detector with the following elements, inputs, and outputs: a control input connected to said control output of said analog-to-digital converter, a data input connected to said data output of said analog-to-digital converter, a first output constituting an output of said compressor, and a second output connected to said second input of said controller, wherein said signal detector comprises a signal noise comparator having a data input, a control input and first and second inputs constituting said data input, said control input and said first and third inputs of said signal detector, a third input and first and second outputs; and an end detector having first and second inputs connected to said first and second outputs of said signal noise comparator, third and fourth inputs constituting said control input and said second input of said signal detector, a first output connected to said third input of said signal noise comparator and constituting said second output of said signal detector and a second output constituting said first output of said signal detector.

Claim 6

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; a controller with a control input, a first input, an output, and an address output; with the control input connected to said control output of said analog-to-digital converter, the first input connected to said second outputs of said data processors, the output connected to said second control inputs of said data processors, and the address output connected to said address inputs of said data processors; and, a signal detector with the following elements, inputs, and outputs: a control input connected to said control output of said analog-to-digital converter, a data input connected to said data output of said analog-to-digital converter, a first output constituting an output of said compressor, and a second output connected to said second input of said controller, wherein said signal detector comprises a signal noise comparator having a data input, a control input and first and second inputs constituting said data input, said control input and said first and third inputs of said signal detector, a third input and first and second outputs; and an end detector having first and second inputs connected to said first and second outputs of said signal noise comparator, third and fourth inputs constituting said control input and said second input of said signal detector, a first output connected to said third input of said signal noise comparator and constituting said second output of said signal detector and a second output constituting said first output of said signal detector.

Claim 7

An information compressor according to claim 3, wherein the signal noise comparator in said signal detector comprises an adder having a data input and an input constituting said data input and said first input of said signal noise comparator, and first and second outputs; a first flip-flop having first and second inputs connected to said first and second outputs of said adder, third and fourth inputs constituting said second and third inputs of said signal noise comparator, and an output constituting said first output of said signal noise comparator; and a second flip-flop having a first input connected to said output of said second flip-flop, second and third inputs constituting said first and third inputs of said signal noise comparator, and an output constituting said second output of said signal noise comparator.

Claim 8

An information compressor according to claim 3, wherein said end detector in said signal detector comprises a first AND gate having first and second inputs constituting said second and fourth inputs of said end detector, and an output; a counter having a first input connected to said output of said AND gate, a second input constituting said first input of said end detector, and an output; an adder having a first input connected to said output of said counter, a second input constituting said third input of said end detector, and an output; a second AND gate having an input connected to said output of said adder and an output; a NOT gate having an input connected to said output of said second AND gate, and an output constituting said first output of said end detector; and a delay element having an input connected to said output of said NOT gate, and an output constituting said second output of said end detector.

Claim 9

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; and a controller with the following elements, inputs, and outputs: a control input connected to said control output of said analog-to-digital converter, a first input connected to said second outputs of said data processors, an output connected to said second control inputs of said data processors, and an address output connected to said address inputs of said data processors, wherein said controller comprises a first counter having a first input, a second input constituting said third input of said controller, and an output; a decoder having a first input connected to said output of said first counter, a second input, and an output constituting said control output of said controller; a signal detection circuit having a first input connected to said output of said first counter, second and third inputs constituting said second and first inputs of said controller, and an output connected to said first input of said first counter and to said second input of said decoder; and a counter having a first input connected to said output of said signal detection circuit, a second input constituting said control input of said controller and an output constituting said address output of said controller.

Claim 10

An information compressor, comprising: an analog-to-digital converter with an input constituting the input of said compressor, a data output, and a control output; multiple data processors with first data inputs, address inputs, first control inputs, second control inputs, and first and second outputs; with the first data inputs connected to said data output of said analog-to-digital converter, first control inputs connected to said control output of said analog-to-digital converter, and first and second outputs constituting first and second outputs of the compressor; and a controller with the following elements, inputs, and outputs: a control input connected to said control output of said analog-to-digital converter, a first input connected to said second outputs of said data processors, an output connected to said second control inputs of said data processors, and an address output connected to said address inputs of said data processors, wherein said controller comprises a first counter having a first input, a second input constituting said third input of said controller, and an output; a decoder having a first input connected to said output of said first counter, a second input, and an output constituting said control output of said controller; a signal detection circuit having a first input connected to said output of said first counter, second and third inputs constituting said second and first inputs of said controller, and an output connected to said first input of said first counter and to said second input of said decoder; and a counter having a first input connected to said output of said signal detection circuit, a second input constituting said control input of said controller and an output constituting said address output of said controller.