Data processing apparatus including a register storing a parameter and a microinstruction execution arrangement including a correction arrangement for causing a first value of the parameter to be change to a second, correct value

Claim 2

A data processing apparatus comprising: memory means for storing microinstructions including a specific microinstruction; microinstruction executing means, coupled to said memory means, for executing a selected one of said microinstructions by a pipeline process and for outputting an operation result, said executing means including register means for storing a parameter having a first value; and microinstruction address generating means for generating an address of said specific microinstruction in said memory means when one of the microinstructions executed by said microinstruction executing means indicates that said specific microinstruction should be executed instead of a currently executed microinstruction if a predetermined event occurs: and control means for having said microinstruction executing means execute said specific microinstruction read from said memory means in response to the address of the specific microinstruction when said predetermined event occurs so that said first value of said parameter is changed to a second, corrected value which should be replaced by said first value of said parameter used in an immediately previous pipeline process; wherein said microinstruction executing means executes said currently-executed microinstruction again using said second, corrected value of said parameter after said second, corrected value is obtained by said correction means.

Claim 3

A data processing apparatus as claimed in claim 1, further comprising data memory means for storing data; wherein said parameter includes an address of a source memory area in said memory means, and data is read out from said source memory area in response to a corresponding one of said microinstructions; and wherein said correction means comprises source address correcting means for having said microinstruction executing means execute said specific microinstruction so that said address of the source memory area obtained when said predetermined event occurs is changed to a corrected source memory address which corresponds to a source memory area used in the immediately previous pipeline process.

Claim 4

A data processing apparatus as claimed in claim 1, further comprising data memory means for storing data; wherein said parameter includes an address of a destination memory area in said memory means, and data is written into said destination memory area in response to a corresponding one of said microinstructions; and wherein said correction means comprises destination address correcting means for having said microinstruction executing means execute said specific microinstruction so that said address of the destination memory area obtained when said predetermined event occur is changed to a corrected destination memory address which corresponds to a destination memory area used in the immediately previous pipeline process.

Claim 5

A data processing apparatus as claimed in claim 1, further comprising data memory means for storing data; wherein said parameter includes number-of-times information showing a number of times that data is transferred from a source memory area in said data memory means to a destination memory area therein in response to a corresponding one of said microinstructions; and wherein said correction means comprises number-of-times information correcting means for having said microinstruction executing means execute said specific microinstruction so that said number-of-times information obtained when said predetermined event occurs is changed to corrected number-of-times information which corresponds to number-of-times information used in the immediately previous process.

Claim 6

A data processing apparatus as claimed in claim 1, wherein said predetermined event includes a request to execute an exception process directed to eliminating an error when said microinstruction executing means is executing said selected one of the microinstructions.

Claim 7

A data processing apparatus as claimed in claim 1, wherein said predetermined event includes an interrupt caused by an external device coupled to said data processing apparatus.

Claim 8

The data processing apparatus as claimed in claim 1, further comprising means for receiving the address of said specific microinstruction and an address of one of the microinstructions other than said specific microinstruction and selecting the address of said specific microinstruction when said predetermined event occurs, so that the specific instruction can be read from the memory means and executed by said microinstruction executing means.

Claim 9

A data processing apparatus comprising: memory means for storing microinstructions including a specific microinstruction; first microinstruction address generating means for generating an address of one of the microinstructions other than said specific microinstruction; microinstruction executing means, coupled to said memory means, for executing one of said microinstructions by a pipeline process and for outputting an operation result, said executing means including register means for storing a parameter having a first value; second microinstruction address generating means for generating an address of said specific microinstruction in said memory means when one of the microinstructions executed by said microinstruction executing means indicates that said specific microinstruction should be executed instead of a currently executed microinstruction if a predetermined event occurs; selecting means for receiving the address of said specific microinstruction from the second microinstruction address generating means and the address of one of the microinstructions from the second microinstruction address generating means and for selecting the address of said specific microinstruction when said predetermined event occurs, wherein: said microinstruction executing mean s executes the specific microinstruction so that said first value of said parameter is changed to a second, corrected value which should be replaced by said first value of said parameter used in an immediately previous pipeline process; and said microinstruction executing means executes said currently-executed microinstruction again using said second, corrected value of said parameter after said second, corrected value is obtained.

Claim 10

A data processing apparatus comprising: memory means for storing microinstructions including a specific microinstruction; first microinstruction address generating means for generating an address of one of the microinstructions other than said specific microinstruction; microinstruction executing means, coupled to said memory means, for executing one of said microinstructions by a pipeline process and for outputting an operation result, said executing means including register means for storing a parameter having a first value; second microinstruction address generating means for generating an address of said specific microinstruction in said memory means when one of the microinstructions executed by said microinstruction executing means indicates that said specific microinstruction should be executed instead of a currently executed microinstruction if a predetermined event occurs; selecting means for receiving the address of said specific microinstruction from the second microinstruction address generating means and the address of one of the microinstructions from the second microinstruction address generating means and for selecting the address of said specific microinstruction when said predetermined event occurs, wherein: said microinstruction executing mean s executes the specific microinstruction so that said first value of said parameter is changed to a second, corrected value which should be replaced by said first value of said parameter used in an immediately previous pipeline process; and said microinstruction executing means executes said currently-executed microinstruction again using said second, corrected value of said parameter after said second, corrected value is obtained.

Claim 11

A data processing apparatus as claimed in claim 8, further comprising source address correcting means for causing said microinstruction executing means to execute said specific microinstruction so that an address of a source memory area obtained when said selecting means selects said specific address is changed to a corrected source memory address which corresponds to the address of a source memory area used in the immediately previous pipeline process.

Claim 12

A data processing apparatus as claimed in claim 9, further comprising memory management means, coupled to said microinstruction executing means and said memory means, for reading out data from said memory means by referring to said parameter and for writing data into said second means by referring to said parameter, and determining means for determining whether or not a predetermined event occurs while said memory management means is reading out data from said memory area and for outputting a control signal to said selecting means when said predetermined event occurs; wherein said selecting means selects said specific address in response to said control signal.

Claim 13

A data processing apparatus as claimed in claim 8, wherein: said parameter includes an address of a destination memory area in said memory means, and data is written into said destination memory area in response to a corresponding one of said microinstructions; and further comprising destination address correcting means for causing said microinstruction executing means to execute said specific microinstruction so that said address of the destination memory area obtained when said selecting means selects said specific address is changed to a corrected destination memory address which corresponds to the address of a destination memory area used in the immediately previous pipeline process.

Claim 14

A data processing apparatus as claimed in claim 11, further comprising memory management means, coupled to said microinstruction executing means and said memory means, for reading out data from said memory means by referring to said parameter and for writing data into said second means by referring to said parameter, and determining means for determining whether or not a predetermined event occurs while said memory management means is writing data into said destination memory area and for outputting a control signal to said selecting means when said predetermined event occurs; wherein said selecting means selects said address of said specific microinstruction in response to said control signal.

Claim 15

A data processing apparatus as claimed in claim 8, wherein: said parameter includes number-of-times information showing a number of times that data is transferred from a memory area in said memory means to a destination memory area therein in response to a corresponding one of said microinstructions; and said microinstruction executing means comprises number-of-times information correcting means for causing said microinstruction executing means to execute said specific microinstruction so that said number-of-times information obtained when said selecting means selects said address of said specific microinstruction is changed to corrected number-of-times information which corresponds to number-of-times information used in the immediately previous pipeline process.

Claim 16

A data processing apparatus as claimed in claim 13, wherein said number-of-times information correcting means comprises increment means for incrementing the number of times that data is transferred by 1.

Claim 17

A data processing apparatus as claimed in claim 13, further comprising determining means for determining whether or not a predetermined event occurs while said memory management means is reading out data from said memory area and for outputting a control signal to said selecting means when said predetermined event occurs; wherein said selecting means selects said address of said specific microinstruction in response to said control signal.

Claim 18

A data processing apparatus as claimed in claim 8, wherein: said parameter includes an address of a destination memory area in said memory means, and data is written into said destination memory area in response to a corresponding one of said microinstructions; and said parameter includes number-of-times information showing a number of times that data is transferred from a memory area in said memory means to a destination memory area therein in response to a corresponding one of said microinstructions; and further comprising correction means, wherein said correction means comprises: address correcting means for causing said microinstruction executing means execute said specific microinstruction so that said address of the memory area obtained when said selecting means selects said specific address is changed to a corrected memory address which corresponds to the address of a memory area used in the immediately previous pipeline process; destination address correcting means for causing said microinstruction executing means to execute said specific microinstruction so that said address of the destination memory area obtained when said selecting means selects said specific address is changed to a corrected destination memory address which corresponds to the address of a destination memory area used in the immediately previous pipeline process; and number-of-times information correcting means for causing said microinstruction executing means to execute said specific microinstruction so that said number-of-times information obtained when said selecting means selects said address of said specific microinstruction is changed to corrected number-of-times information which corresponds to number-of-times information used in the immediately previous pipeline process.

Claim 19

A data processing apparatus as claimed in claim 8, wherein said specific address is generated when a request to execute an exception process directed to eliminating an error occurs while said microinstruction executing means is executing said selected one of the microinstructions.

Claim 20

A data processing apparatus as claimed in claim 8, wherein said specific address is generated when an interrupt is generated by an external device coupled to said data processing apparatus while said microinstruction executing means is executing said selected one of the microinstructions.

Claim 21

A data processing apparatus as claimed in claim 8, wherein said microinstructions include an exception process microinstruction directed to eliminating an error which occurs while said microinstruction executing means is executing said selected one of the microinstructions, and wherein said means comprises means for causing said microinstruction executing means to execute said exception process microinstruction after said specific microinstruction is executed.