Method and apparatus for serial data communications using FIFO buffers

Claim 1

A serial communications circuit coupled to a data processing system and a serial port comprising: a) a first serial receiver and transmitter coupled to the serial port for receiving and transmitting serial data; b) a transmit buffer coupled to the first serial receiver and transmitter for temporarily storing transmit data from the data processing system, and for providing said transmit data to the first serial receiver and transmitter; c) a receive buffer coupled to the first serial receiver and transmitter for temporarily storing received data from the serial port and for providing said data to the data processing system; d) a transmit register associated with the transmit buffer for storing a first pre-determined value, said first pre-determined value indicating the maximum capacity of the transmit buffer; e) a receive register associated with the receive buffer for storing a second pre-determined value, said second pre-determined value indicating the maximum capacity of the receive buffer; f) a transmit counter for maintaining a transmit buffer count, said transmit buffer count indicating the current amount of data in the transmit buffer; g) a receive counter for maintaining a receive buffer count, said receive buffer count indicating a current amount of data in the receive buffer; and h) a data flow controller coupled to the first serial receiver and transmitter, the transmit buffer, the receive buffer, the transmit register, the receive register, the transmit counter, and the receive counter for allowing data to flow into the transmit and receive buffers when the transmit buffer count is less than the first pre-determined value and the receive buffer count is less than the second pre-determined value, and when the transmit buffer count and the receive buffer count exceeds or is equal to the first pre-determined value and the second pre-determined value, respectively, for stopping data flow into the transmit and receive buffers and for transferring the transmit data and receive data to the serial port and the data processing system, respectively; wherein the data controller interrupts the data processing system based on the transmit buffer count and the receive buffer count; and wherein the transmit register and the receive register are programmable by the data processing system such that the data processing system may control the frequency at which the data processing system is interrupted by the data controller by changing the first and second pre-determined values so that the interrupt frequency is based upon a current data transfer rate between the data processing system and the serial port and a current loading of the data processing system.