Switching apparatus for ATM

Claim 2

A switching apparatus comprising: an input port to which information data associated with an ATM cell is input; storage means for storing the information data input via said input port; procedure information means for outputting procedure information indicating a procedure for sequentially performing frame synchronization process for finding each frame of the information data read out from said storage means and ATM cell synchronization process for checking a cell structure; process means for sequentially performing the frame synchronization process and the cell synchronization process with respect to the information data read out from said storage means in accordance with the procedure information from said procedure information means; and an output port for outputting information data processed by said process means.

Claim 3

An apparatus according to claim 1, wherein said process means sequentially executes the frame synchronization process and the ATM cell synchronization process when a predetermined amount of information data is stored in said storage means.

Claim 4

An apparatus according to claim 2, wherein said output port includes output side storage means for temporarily storing information data after the frame synchronization process and the ATM cell synchronization process, and said process means stores information data of a predetermined pattern when information data stored in said output side storage means is smaller than a predetermined data amount.

Claim 5

An apparatus according to claim 1, wherein said input port is composed of an input FIFO for temporarily storing information data, and said process means executes said frame synchronizing process and said cell synchronization process when the amount of data stored in said input FIFO is larger than a predetermined amount of data.

Claim 6

An apparatus according to claim 4, wherein said apparatus temporarily writes the information data from said input FIFO into said storage means, and thereafter transfers a pointer for a data block to the process means for use by the frame synchronization process, the pointer being stored in the storage means and indicates a position at which the data block is stored.

Claim 7

An apparatus according to claim 1, wherein said procedure information means further outputs information indicating the procedure for counting the cells inputted from said input port and information indicating the procedure for measuring the cell arrival interval for each connection set for said input port, regarding the number of cells inputted as the elapsed time at said input port; and said process means further executes said counting of cells inputted and said measurement of cell arrival interval on the basis of the information from said procedure information means, soon after said frame synchronization process and cell synchronization process.

Claim 8

An apparatus according to claim 6, wherein said procedure information means further outputs information indicating the procedure for judging whether to transmit said inputted cells to said output port, on the basis of the cell arrival interval between the individual cells inputted from said input port and the information previously stored in said storage means; and said process means further executes the process of judging whether to transmit said inputted cells on the basis of the procedure information from said procedure information means, soon after said counting of cells inputted and said measurements of cell arrival interval.

Claim 9

An apparatus according to claim 1, wherein said procedure information means further outputs information indicating the procedure for monitoring the progress of said frame synchronization process and said cell synchronization process; and said process means executes said monitoring procedure according to the procedure information from said procedure information means, during the time when neither said frame synchronization process nor said cell synchronization process is being performed.

Claim 10

An apparatus according to claim 1, wherein said procedure information means further outputs information indicating an OAM cell extracting procedure for extracting OAM cells from the cells obtained from said cell synchronization process, an OAM cell diverging procedure for writing said extracted OAM cells into OAM cell storage means, and an OAM cell process procedure for processing said diverged OAM cells; and said process means sequentially executes said OAM cell extracting procedure, OAM cell diverging procedure, and OAM cell process procedure according to the procedure information from said procedure information means, during the time when neither said frame synchronization process nor said cell synchronization process is being performed, and said OAM cell storage means transfers a pointer for a data block to the process means for use by said OAM cell process procedure, the pointer being stored in said OAM cell storage means and indicates a position at which the data block is stored.

Claim 11

A switching apparatus comprising: an input port having an input FIFO for receiving a bit string constituting information data associated with ATM cell and temporarily holding the bit string; a processor for sequentially performing frame synchronization process of searching the bit string stored in said input FIFO for a bit pattern indicating a head of a frame by referring to said input FIFO, and checking whether the bit pattern indicating the head of the frame is present a frame length ahead of the frame, and cell synchronization process of finding a bit pattern indicating a head of a frame in the input bit string, and recognizing a head of a cell from the bit pattern and processing information data in units of cells when the bit pattern sequentially appears at intervals of the frame length; and an output port having an output FIFO for temporarily storing and outputting information indicating a destination of a cell stream formed by said processor.

Claim 12

A switching apparatus comprising: an input port having an input FIFO for receiving a bit string constituting information data associated with ATM cell and temporarily holding the bit string; a processor for sequentially performing frame synchronization process of searching the bit string stored in said input FIFO for a bit pattern indicating a head of a frame by referring to said input FIFO, and checking whether the bit pattern indicating the head of the frame is present a frame length ahead of the frame, and cell synchronization process of finding a bit pattern indicating a head of a frame in the input bit string, and recognizing a head of a cell from the bit pattern and processing information data in units of cells when the bit pattern sequentially appears at intervals of the frame length; and an output port having an output FIFO for temporarily storing and outputting information indicating a destination of a cell stream formed by said processor.

Claim 13

An apparatus according to claim 10, wherein said processor sequentially executes said frame synchronization process and said ATM cell synchronization process, when a predetermined amount of data has been stored in said input FIFO.

Claim 14

An apparatus according to claim 11, wherein said processor inserts information data of a predetermined pattern in said output FIFO when information data stored in said output FIFO is smaller than a predetermined data amount.

Claim 15

A switching apparatus comprising: an input port to which ATM cells are inputted; storage means for storing said ATM cells inputted via said input port; procedure information means for outputting information indicating the procedure for HEC operation and the mapping of said ATM cells onto a frame structure, to said ATM cells read from said storage means; process means for performing said HEC operation and said ATM cell mapping onto a frame structure on the ATM cells stored in said storage means, on the basis of the procedure information from said procedure information means; and an output port for outputting the ATM cells mapped on a frame structure at said process means.

Claim 16

A switching apparatus comprising: an input port to which ATM cells are inputted; storage means for storing said ATM cells inputted via said input port; procedure information means for outputting information indicating the procedure for HEC operation and the mapping of said ATM cells onto a frame structure, to said ATM cells read from said storage means; process means for performing said HEC operation and said ATM cell mapping onto a frame structure on the ATM cells stored in said storage means, on the basis of the procedure information from said procedure information means; and an output port for outputting the ATM cells mapped on a frame structure at said process means.

Claim 17

An apparatus according to claim 13, wherein said output port contains output-side storage means for temporarily storing the resulting information data after said HEC operation and said ATM cell mapping onto a frame structure; and said process means for mapping the ATM cells of a predetermined pattern onto a frame structure and storing the results in said output-side storage means, when the amount of information data stored in said output-side means is less than a predetermined amount of data.

Claim 18

A switching apparatus comprising: an input port to which ATM cells with routing tags are inputted; storage means for storing said ATM cells with routing tags inputted via said input port; procedure information means for outputting procedure information indicating the procedure for routing tag deletion, HEC operation and ATM cell mapping onto a frame structure, to said ATM cells with routing tags read from said storage means; process means for performing said routing tag deletion, said HEC operation, and said ATM cell mapping onto a frame structure on the ATM cells stored in said storage means, on the basis of the procedure information from said procedure information means; and an output port for outputting the ATM cells mapped on a frame structure at said process means.

Claim 19

A switching apparatus comprising: an input port to which ATM cells with routing tags are inputted; storage means for storing said ATM cells with routing tags inputted via said input port; procedure information means for outputting procedure information indicating the procedure for routing tag deletion, HEC operation and ATM cell mapping onto a frame structure, to said ATM cells with routing tags read from said storage means; process means for performing said routing tag deletion, said HEC operation, and said ATM cell mapping onto a frame structure on the ATM cells stored in said storage means, on the basis of the procedure information from said procedure information means; and an output port for outputting the ATM cells mapped on a frame structure at said process means.

Claim 20

An apparatus according to claim 15, wherein said input port comprises an input FIFO for temporarily storing information data associated with the ATM cells, and said process means sequentially executes said routing tag deletion, said HEC operation, and said ATM cell mapping onto a frame structure, when a predetermined amount of ATM cells with routing tags is stored in said storage means.

Claim 21

An apparatus according to claim 16, wherein said apparatus temporarily writes the ATM cells with routing tags from said input FIFO into said storage means, and thereafter transfers a pointer for a data block to the process means for use during the process of mapping ATM cells, the pointer being stored in said storage means and indicates a position at which the ATM cells are stored.

Claim 22

An apparatus according to claim 15, wherein said procedure information means further outputs information indicating an OAM cell extracting procedure for extracting OAM cells from the cells obtained as a result from deleting said routing tags, an OAM cell diverging procedure for writing said extracted OAM cells into OAM cell storage means, and an OAM cell process procedure for processing said diverged OAM cells; and said process means sequentially executes said OAM cell extracting procedure, OAM cell diverging procedure, and OAM cell process procedure according to the procedure information from said procedure information means during the time when neither said routing tag deletion nor said HEC operation nor said ATM cell mapping onto a frame structure is being performed, and transfers the pointer to said OAM cell storage means from said OAM cell diverging procedure to said OAM cell process procedure.

Claim 23

A switching apparatus comprising: an input port containing an input FIFO for receiving ATM cells with routing tags and temporarily storing them; a processor for referring to said input FIFO, deleting the routing tags from the ATM cells stored therein, creating a frame structure on its own, and then mapping said ATM cells from which said routing tags have been deleted, onto said created frame structure; and an output port containing an FIFO for temporarily storing the frame created by said processor and outputs the frame.

Claim 24

A switching apparatus comprising: an input port containing an input FIFO for receiving ATM cells with routing tags and temporarily storing them; a processor for referring to said input FIFO, deleting the routing tags from the ATM cells stored therein, creating a frame structure on its own, and then mapping said ATM cells from which said routing tags have been deleted, onto said created frame structure; and an output port containing an FIFO for temporarily storing the frame created by said processor and outputs the frame.

Claim 25

An apparatus according to claim 19, wherein said processor sequentially executes said routing tag deletion, said frame structure creation, and said ATM cell mapping onto a frame structure, when a predetermined amount of ATM cells is stored in said input FIFO.

Claim 26

An apparatus according to claim 19, wherein said processor maps the ATM cells of a predetermined pattern onto a frame and then inserts the results into said output FIFO, when the amount of information data stored in said output FIFO is less than a predetermined amount of data.

Claim 27

A switching apparatus comprising: storage means for storing cell headers of ATM cells; procedure information means for outputting procedure information indicating the procedure for inputting the cell headers from said storing means; procedure information means for outputting procedure information indicating a process for inputting the cell headers from said storing means, information indicating a process for counting the cell headers inputted from said storing means, information indicating a process for measuring a cell arrival interval for each connection set for said storing means and regarding the number of cell headers inputted as an elapsed time, information indicating a process for judging whether or not the inputted cell headers are to be transmitted, and information indicating a process for rewriting the cell headers determined to be transmitted; and process means for sequentially performing the process of inputting the cell headers from said storing means, the process of counting the cell headers inputted from said storing means, the process of measuring the cell arrival interval for each connection set for said storing means regarding the number of cell headers inputted as the elapsed time, the process of judging whether or not the inputted cell headers are to be transmitted, and the process of rewriting the cell headers determined to be transmitted.

Claim 28

A switching apparatus comprising: storage means for storing cell headers of ATM cells; procedure information means for outputting procedure information indicating the procedure for inputting the cell headers from said storing means; procedure information means for outputting procedure information indicating a process for inputting the cell headers from said storing means, information indicating a process for counting the cell headers inputted from said storing means, information indicating a process for measuring a cell arrival interval for each connection set for said storing means and regarding the number of cell headers inputted as an elapsed time, information indicating a process for judging whether or not the inputted cell headers are to be transmitted, and information indicating a process for rewriting the cell headers determined to be transmitted; and process means for sequentially performing the process of inputting the cell headers from said storing means, the process of counting the cell headers inputted from said storing means, the process of measuring the cell arrival interval for each connection set for said storing means regarding the number of cell headers inputted as the elapsed time, the process of judging whether or not the inputted cell headers are to be transmitted, and the process of rewriting the cell headers determined to be transmitted.