Apparatus and method for performing asynchronous multi-standard VBI data extraction

Claim 2

A circuit for decoding Vertical Blanking Interval (VBI) television data having any one of a plurality of VBI formats, comprising: an input circuit coupled to receive a television signal and to output in response thereto digital VBI data at a data frequency; a register coupled to receive and store the VBI data; a programmable clock generator receiving a program signal and generating a clock signal having a frequency determined by the program signal, wherein the clock signal is asynchronous with the VBI data; and a control circuit coupled to receive the VBI data, the clock signal, and a format signal indicating which VBI format is to be decoded, wherein the control circuit provides the program signal based on the format signal, and wherein the control circuit provides a sample signal at the data frequency in response to the clock signal and the VBI data to cause the register to load VBI data at approximately the midpoint in time of each bit of VBI data.

Claim 3

The circuit of claim 1, wherein the frequency of the clock is an integer multiple of the data frequency.

Claim 4

The circuit of claim 1, wherein the control circuit comprises a state machine coupled to receive the clock and the VBI data and generating in response thereto the sample signal.

Claim 5

The circuit of claim 3, wherein the control circuit further comprises: a line counter coupled to receive line synchronization data from the television signal, wherein the line counter outputs a current line number based on the synchronization data; a register interface to receive and store format data from the format signal; and a comparator coupled to receive an output of the register interface and the current line number, the comparator generating an enable signal when the current line number corresponds to the format data; wherein the state machine is further coupled to receive the enable signal, such that the sample signal is generated in response to the clock while the enable signal is asserted.

Claim 6

The circuit of claim 3, wherein the control circuit further comprises an input/output circuit coupled to the state machine and the register to signal a host processor and enable the register to output when the register is fully loaded.

Claim 7

The circuit of claim 1, wherein the input circuit comprises a fast comparator for converting the television signal to digital VBI data.

Claim 8

The circuit of claim 1, wherein the clock generator comprises a crystal oscillator.

Claim 9

The circuit of claim 7, wherein the clock generator is a phase-locked loop.

Claim 10

A circuit for decoding Vertical Blanking Interval (VBI) television data having any one of a plurality of VBI formats, comprising: an input circuit coupled to receive a television signal and to output in response thereto digital VBI data at a data frequency, the VBI data including a plurality of bits, each having a data interval; a shift register coupled to receive and store the VBI data; a programmable clock generator receiving a program signal and generating a clock signal having a clock frequency which is an integer multiple of the data frequency, wherein the clock signal is asynchronous relative to the television signal and wherein the clock frequency is determined by the program signal; and a control circuit coupled to receive a format signal indicating which VBI format is to be decoded, the clock signal, the digital VBI data, a horizontal sync signal, and a vertical sync signal, wherein the control circuit provides: the program signal to the clock generator based on the format signal; and a sample signal to the shift register at the data frequency in response to the clock signal and based on the format signal and the horizontal and vertical sync signals, to load the VBI data into the shift register at approximately the middle of the data interval of each bit of VBI data by counting cycles of the clock signal, such that valid VBI data is extracted from the television signal.

Claim 11

A circuit for decoding Vertical Blanking Interval (VBI) television data having any one of a plurality of VBI formats, comprising: an input circuit coupled to receive a television signal and to output in response thereto digital VBI data at a data frequency, the VBI data including a plurality of bits, each having a data interval; a shift register coupled to receive and store the VBI data; a programmable clock generator receiving a program signal and generating a clock signal having a clock frequency which is an integer multiple of the data frequency, wherein the clock signal is asynchronous relative to the television signal and wherein the clock frequency is determined by the program signal; and a control circuit coupled to receive a format signal indicating which VBI format is to be decoded, the clock signal, the digital VBI data, a horizontal sync signal, and a vertical sync signal, wherein the control circuit provides: the program signal to the clock generator based on the format signal; and a sample signal to the shift register at the data frequency in response to the clock signal and based on the format signal and the horizontal and vertical sync signals, to load the VBI data into the shift register at approximately the middle of the data interval of each bit of VBI data by counting cycles of the clock signal, such that valid VBI data is extracted from the television signal.

Claim 12

A circuit for decoding Vertical Blanking Interval (VBI) television data having any one of a plurality of VBI formats, comprising: input means coupled to receive a television signal for outputting digital VBI data at a data frequency in response to the television signal; storage means for receiving and storing the VBI data; clock generator means for generating a clock signal in response to a program signal, the clock signal having a frequency determined by the program signal, wherein the clock signal is asynchronous with the VBI data; and control means coupled to receive the VBI data, the clock signal, and a format signal indicating which VBI format is to be decoded, for providing the program signal based on the format signal and for providing a sample signal at the data frequency in response to the clock signal and the VBI data to cause the VBI data to be loaded into the storage means at approximately the midpoint in time of each bit of VBI data.

Claim 13

A circuit for decoding Vertical Blanking Interval (VBI) television data having any one of a plurality of VBI formats, comprising: input means coupled to receive a television signal for outputting digital VBI data at a data frequency in response to the television signal; storage means for receiving and storing the VBI data; clock generator means for generating a clock signal in response to a program signal, the clock signal having a frequency determined by the program signal, wherein the clock signal is asynchronous with the VBI data; and control means coupled to receive the VBI data, the clock signal, and a format signal indicating which VBI format is to be decoded, for providing the program signal based on the format signal and for providing a sample signal at the data frequency in response to the clock signal and the VBI data to cause the VBI data to be loaded into the storage means at approximately the midpoint in time of each bit of VBI data.

Claim 14

The circuit of claim 10, wherein the frequency of the clock is an integer multiple of the data frequency.

Claim 15

The circuit of claim 10, wherein the control means comprises state machine means coupled to receive the clock and the VBI data and generating in response thereto the sample signal.

Claim 16

The circuit of claim 12, wherein the control means further comprises: line counter means coupled to receive line synchronization data from the television signal for outputting a current line indication based on the synchronization data; interface means for receiving and storing format data from the format signal; and comparator means coupled to receive an output of the interface means and the current line indication for generating an enable signal when the current line indication corresponds to the format data; and state machine means coupled to receive the enable signal, for generating the sample signal in response to the clock signal while the enable signal is asserted.

Claim 17

The circuit of claim 10, wherein the input means comprises comparator means for converting the television signal to digital VBI data.

Claim 18

The circuit of claim 10, wherein the clock generator means comprises a crystal oscillator.

Claim 19

A circuit for extracting Vertical Blanking Interval (VBI) data having any one of a plurality of VBI formats from a television signal, comprising: means for selecting one of the VBI formats to be decoded; means for converting the television signal into digital form, wherein the television signal includes VBI data including a plurality of bits at a data frequency that corresponds to the selected format; means for providing a clock that is asynchronous with the television signal at a clock frequency that is an integer multiple of the data frequency; and means for sampling the VBI data in response to the clock at the data frequency at approximately the midpoint in time of each bit of VBI data.

Claim 20

A circuit for extracting Vertical Blanking Interval (VBI) data having any one of a plurality of VBI formats from a television signal, comprising: means for selecting one of the VBI formats to be decoded; means for converting the television signal into digital form, wherein the television signal includes VBI data including a plurality of bits at a data frequency that corresponds to the selected format; means for providing a clock that is asynchronous with the television signal at a clock frequency that is an integer multiple of the data frequency; and means for sampling the VBI data in response to the clock at the data frequency at approximately the midpoint in time of each bit of VBI data.

Claim 21

The circuit of claim 16, wherein the means for providing a clock comprises means for establishing the clock frequency based on the selected format.

Claim 22

The circuit of claim 16, wherein the means for sampling comprises: means for waiting for an occurrence of a start bit in the VBI data; means for counting, upon the occurrence of the start bit, N cycles of the clock, where N is an integer substantially equal to one-half the integer multiple; and means for repeatedly sampling, beginning at the end of the Nth cycle of the clock following the occurrence of the start bit, the VBI data at the data frequency.

Claim 23

The circuit of claim 16, further comprising means for storing the sampled VBI data in a storage device.

Claim 26

The method of claim 20, wherein the step of providing a clock comprises the step of establishing the clock frequency based on the selected format.

Claim 27

The method of claim 20, wherein the step of sampling comprises the steps of: waiting for an occurrence of a start bit in the VBI data; upon the occurrence of the start bit, counting N cycles of the clock, where N is an integer substantially equal to one-half the integer multiple; and beginning at the end of the Nth cycle of the clock following the occurrence of the start bit, repeatedly sampling the VBI data at the data frequency.

Claim 28

The method of claim 20, further comprising the step of storing the sampled VBI data in a storage device.

Claim 29

A computer system having a processor, a memory, at least one input/output device, and video capture circuitry for receiving and decoding a television signal, the video capture circuitry including extraction circuitry for extracting VBI data in the television signal, the extraction circuitry comprising: an input circuit coupled to receive the television signal and to output in response thereto digital VBI data at a data frequency; a register coupled to receive and store the VBI data; a programmable clock generator receiving a program signal and generating a clock signal having a frequency determined by the program signal, wherein the clock signal is asynchronous with the VBI data; and a control circuit coupled to receive the VBI data, the clock signal, and a format signal indicating which VBI format is to be decoded, wherein the control circuit provides the program signal based on the format signal, and wherein the control circuit provides a sample signal at the data frequency in response to the clock signal and the VBI data to cause the register to load VBI data at approximately the midpoint in time of each bit of VBI data.

Claim 30

A computer system having a processor, a memory, at least one input/output device, and video capture circuitry for receiving and decoding a television signal, the video capture circuitry including extraction circuitry for extracting VBI data in the television signal, the extraction circuitry comprising: an input circuit coupled to receive the television signal and to output in response thereto digital VBI data at a data frequency; a register coupled to receive and store the VBI data; a programmable clock generator receiving a program signal and generating a clock signal having a frequency determined by the program signal, wherein the clock signal is asynchronous with the VBI data; and a control circuit coupled to receive the VBI data, the clock signal, and a format signal indicating which VBI format is to be decoded, wherein the control circuit provides the program signal based on the format signal, and wherein the control circuit provides a sample signal at the data frequency in response to the clock signal and the VBI data to cause the register to load VBI data at approximately the midpoint in time of each bit of VBI data.

Claim 31

The computer system of claim 24, wherein the control circuit comprises a state machine coupled to receive the clock and the VBI data and generating in response thereto the sample signal.

Claim 32

The computer system of claim 25, wherein the control circuit further comprises: a line counter coupled to receive line synchronization data from the television signal, wherein the line counter outputs a current line number based on the synchronization data; a register interface to receive and store format data from the format signal; a comparator coupled to receive an output of the register interface and the current line number, the comparator generating an enable signal when the current line number corresponds to the format data; and wherein the state machine is further coupled to receive the enable signal, such that the sample signal is generated in response to the clock while the enable signal is asserted.

Claim 33

A computer system having a processor, a memory, at least one input/output device, and video capture circuitry for receiving and decoding a television signal, the video capture circuitry including extraction means for extracting VBI data in the television signal, the extraction means comprising: input means coupled to receive the television signal for outputting in response thereto digital VBI data at a data frequency, the VBI data including a plurality of bits, each having a data interval; register means coupled to the input means for storing the VBI data; clock generator means for receiving a program signal and generating a clock signal having a clock frequency which is an integer multiple of the data frequency, wherein the clock signal is asynchronous relative to the television signal and wherein the clock frequency is determined by the program signal; and control means, coupled to receive a format signal indicating which VBI format is to be decoded, the clock signal, the VBI data, a horizontal sync signal, and a vertical sync signal, for providing: the program signal to the clock generator means based on the format signal; and a sample signal to the register means at the data frequency in response to the clock signal and based on the format signal and the horizontal and vertical sync signals, to load the VBI data into the register means at approximately the middle of the data interval of each bit of VBI data by counting cycles of the clock signal, such that valid VBI data is extracted from the television signal.

Claim 34

A computer system having a processor, a memory, at least one input/output device, and video capture circuitry for receiving and decoding a television signal, the video capture circuitry including extraction means for extracting VBI data in the television signal, the extraction means comprising: input means coupled to receive the television signal for outputting in response thereto digital VBI data at a data frequency, the VBI data including a plurality of bits, each having a data interval; register means coupled to the input means for storing the VBI data; clock generator means for receiving a program signal and generating a clock signal having a clock frequency which is an integer multiple of the data frequency, wherein the clock signal is asynchronous relative to the television signal and wherein the clock frequency is determined by the program signal; and control means, coupled to receive a format signal indicating which VBI format is to be decoded, the clock signal, the VBI data, a horizontal sync signal, and a vertical sync signal, for providing: the program signal to the clock generator means based on the format signal; and a sample signal to the register means at the data frequency in response to the clock signal and based on the format signal and the horizontal and vertical sync signals, to load the VBI data into the register means at approximately the middle of the data interval of each bit of VBI data by counting cycles of the clock signal, such that valid VBI data is extracted from the television signal.