Semiconductor device having improved coverage with increased wiring layers

Claim 2

A semiconductor device comprising: a base film having a principal surface; an interlayer insulating region, formed on the principal surface of said base film, in which first and second conductive sections are formed, said interlayer insulating region having first and second contact holes which reach the first and the second conductive sections, respectively, said interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first conductive section; a first conductive region, connected with said first conductor, covering the upper surface of said interlayer insulating region, said first conductive region having an upper surface and a side surface; an insulating film covering only the upper surface and the side-wall surface of said first conductive region, but not extending beyond the side-wall surface of said first conductive region onto the upper surface of said interlayer insulating region; a second conductor, embedded in the second contact hole, for connecting with said second conductive section; and a second conductive region covering said second conductor, the upper surface of said interlayer insulating region, and said insulating film, said second conductive region in direct contact with the upper surface of said interlayer insulating region, whereby said second conductive region overlies said first conductive region with said second conductive region isolated from said first conductive region by said insulating film.

Claim 3

A semiconductor device as claimed in claim 1, wherein each of said first conductive region, and said first and said second conductors consists essentially of polysilicon.

Claim 4

A semiconductor device as claimed in claim 1 wherein said first conductive region comprises a polysilicon film which consists essentially of polysilicon, said polysilicon film having an upper surface, and a high melting-point metal silicide film formed on the upper surface of said polysilicon film.

Claim 5

A semiconductor device as claimed in claim 3, wherein said high melting-point metal silicide film consists of a tungsten silicide film.

Claim 6

A semiconductor device as claimed in claim 1, wherein said first and said second conductive sections compose an n-th wiring layer formed on said base insulating film where n represents a natural number, said first conductive region composing an (n+1)-th wiring layer, and said second conductive region composing an (n+2)-th wiring layer.

Claim 7

A semiconductor device as claimed in claim 1, wherein said interlayer insulating region comprises a first interlayer insulating film formed on the principal surface of said base film and a second interlayer insulating film formed on the first interlayer insulating film, said first conductive section being formed on the principal surface of the base film, said second conductive section being formed on the first interlayer insulating film, the first contact hole being bored in both the first interlayer insulating film and the second interlayer insulating film, the second contact hole being bored in the second interlayer insulating film alone.

Claim 8

A semiconductor device as claimed in claim 1, wherein said interlayer insulating region comprises a first interlayer insulating film formed on the principal surface of said base film and a second interlayer insulating film formed on the first interlayer insulating film, said first conductive section being formed on the first interlayer insulating film, said second conductive section being formed on the principal surface of said base film, the first contact hole being bored in the second interlayer insulating film alone, the second contact hole being bored in both the first interlayer insulating film and the second interlayer insulating film.

Claim 9

A semiconductor device as claimed in claim 1, wherein said base film is a semiconductor substrate, the first and the second conductive sections being first and second impurity regions formed on the semiconductor substrate, respectively.

Claim 10

A semiconductor device as claimed in claim 8, wherein the first impurity region is one of source/drain regions, the second impurity region being another of the source/drain regions, said first conductive region being composed of a bit line which connects with the first impurity region through said first conductor, said second conductive region being composed of a storage lower electrode which connects with the second impurity region through said second conductor.

Claim 11

A semiconductor device comprising: a base insulating film having a principal surface; first and second lower wiring sections formed on the principal surface of said base insulating film; an interlayer insulating region, formed on the principal surface of said base insulating film, covering said first and second lower wiring sections, said interlayer insulating region having first and second contact holes which reach said first and said second lower wiring sections, respectively, said interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first lower wiring section; a first upper wiring section, connected with said first conductor, covering the upper surface of said interlayer insulating region, said first upper wiring section having an upper surface and a side surface; an insulating film covering only the upper surface and the side-wall surface of said first upper wiring section, but not extending beyond the side-wall surface of said first upper wiring section onto the upper surface of said interlayer insulating region; a second conductor, embedded in the second contact hole, for connecting with said second lower wiring section; and a second upper wiring section covering said second conductor, the upper surface of said interlayer insulating region, and said insulating film, said second upper wiring section in direct contact with the upper surface of said interlayer insulating region, whereby said second upper wiring section overlies said first upper wiring section with said second upper wiring section isolated from said first upper wiring section by said insulating film.

Claim 12

A semiconductor device comprising: a base insulating film having a principal surface; first and second lower wiring sections formed on the principal surface of said base insulating film; an interlayer insulating region, formed on the principal surface of said base insulating film, covering said first and second lower wiring sections, said interlayer insulating region having first and second contact holes which reach said first and said second lower wiring sections, respectively, said interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first lower wiring section; a first upper wiring section, connected with said first conductor, covering the upper surface of said interlayer insulating region, said first upper wiring section having an upper surface and a side surface; an insulating film covering only the upper surface and the side-wall surface of said first upper wiring section, but not extending beyond the side-wall surface of said first upper wiring section onto the upper surface of said interlayer insulating region; a second conductor, embedded in the second contact hole, for connecting with said second lower wiring section; and a second upper wiring section covering said second conductor, the upper surface of said interlayer insulating region, and said insulating film, said second upper wiring section in direct contact with the upper surface of said interlayer insulating region, whereby said second upper wiring section overlies said first upper wiring section with said second upper wiring section isolated from said first upper wiring section by said insulating film.

Claim 13

A semiconductor device as claimed in claim 10, wherein each of said first upper wiring section, and said first and said second conductors consists essentially of polysilicon.

Claim 14

A semiconductor device as claimed in claim 10, wherein said first upper wiring section comprises a polysilicon film which consists essentially of polysilicon, said polysilicon film having an upper surface, and a high melting-point metal silicide film formed on the upper surface of said polysilicon film.

Claim 15

A semiconductor device as claimed in claim 12, wherein said high melting-point metal silicide film consists of a tungsten silicide film.

Claim 16

A semiconductor device comprising: a base insulating film having a principal surface; first lower wiring sections formed on the principal surface of said base insulating film; an first interlayer insulating film which is formed on the principal surface of said base insulating film and which covers said first lower wiring section; second lower wiring sections formed on said first interlayer insulating film; a second interlayer insulating film which is formed on said first interlayer insulating film and which covers said second lower wiring section, both said first interlayer insulating film and said second interlayer insulating films having a first contact hole which reaches said first lower wiring section, only said second interlayer insulating film having a second contact hole which reaches said second lower wiring section, said second interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first lower wiring section; a first upper wiring section, connected with said first conductor, covering the upper surface of said second interlayer insulating region, said first upper wiring section having an upper surface and a side surface; a third insulating film covering only the upper surface and the side-wall surface of said first upper wiring section, but not extending beyond the side-wall surface of said first upper wiring section onto the upper surface of said second interlayer insulating film; a second conductor, embedded in the second contact hole, for connecting with said second lower wiring section; and a second upper wiring section covering said second conductor, the upper surface of said second interlayer insulating region, and said third insulating film, said second upper wiring section in direct contact with the upper surface of said second interlayer insulating film, whereby said second upper wiring section overlies said first upper wiring section with said second upper wiring section isolated from said first upper wiring section by said third insulating film.

Claim 17

A semiconductor device comprising: a base insulating film having a principal surface; first lower wiring sections formed on the principal surface of said base insulating film; an first interlayer insulating film which is formed on the principal surface of said base insulating film and which covers said first lower wiring section; second lower wiring sections formed on said first interlayer insulating film; a second interlayer insulating film which is formed on said first interlayer insulating film and which covers said second lower wiring section, both said first interlayer insulating film and said second interlayer insulating films having a first contact hole which reaches said first lower wiring section, only said second interlayer insulating film having a second contact hole which reaches said second lower wiring section, said second interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first lower wiring section; a first upper wiring section, connected with said first conductor, covering the upper surface of said second interlayer insulating region, said first upper wiring section having an upper surface and a side surface; a third insulating film covering only the upper surface and the side-wall surface of said first upper wiring section, but not extending beyond the side-wall surface of said first upper wiring section onto the upper surface of said second interlayer insulating film; a second conductor, embedded in the second contact hole, for connecting with said second lower wiring section; and a second upper wiring section covering said second conductor, the upper surface of said second interlayer insulating region, and said third insulating film, said second upper wiring section in direct contact with the upper surface of said second interlayer insulating film, whereby said second upper wiring section overlies said first upper wiring section with said second upper wiring section isolated from said first upper wiring section by said third insulating film.

Claim 18

A semiconductor device as claimed in claim 14, wherein said first upper wiring section comprises a polysilicon film which consists essentially of polysilicon, said polysilicon film having an upper surface, and a high melting-point metal silicide film formed on the upper surface of said polysilicon film.

Claim 19

A semiconductor device as claimed in claim 15, wherein said high melting-point metal silicide film consists of a tungsten silicide film.

Claim 20

A semiconductor device comprising: a base insulating film having a principal surface; first lower wiring sections formed on the principal surface of said base insulating film; an first interlayer insulating film which is formed on the principal surface of said base insulating film and which covers said first lower wiring section; second lower wiring sections formed on said first interlayer insulating film; a second interlayer insulating film which is formed on said first interlayer insulating film and which covers said second lower wiring section, only said second interlayer insulating film having a first contact hole which reaches said second lower wiring section, both said first interlayer insulating film and said second interlayer insulating films having a second contact hole which reaches said first lower wiring section, said second interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said second lower wiring section; a first upper wiring section, connected with said first conductor, covering the upper surface of said second interlayer insulating region, said first upper wiring section having an upper surface and a side surface; a third insulating film covering only the upper surface and the side-wall surface of said first upper wiring section but not extending beyond the side-wall surface of said first upper wiring section onto the upper surface of said second interlayer insulating film; a second conductor, embedded in the second contact hole, for connecting with said first lower wiring section; and a second upper wiring section covering said second conductor, the upper surface of said second interlayer insulating region, and said third insulating film, said second upper wiring section in direct contact with the upper surface of said second interlayer insulating film, whereby said second upper wiring section overlies said first upper wiring section with said second upper wiring section isolated from said first upper wiring section by said third insulating film.

Claim 21

A semiconductor device comprising: a base insulating film having a principal surface; first lower wiring sections formed on the principal surface of said base insulating film; an first interlayer insulating film which is formed on the principal surface of said base insulating film and which covers said first lower wiring section; second lower wiring sections formed on said first interlayer insulating film; a second interlayer insulating film which is formed on said first interlayer insulating film and which covers said second lower wiring section, only said second interlayer insulating film having a first contact hole which reaches said second lower wiring section, both said first interlayer insulating film and said second interlayer insulating films having a second contact hole which reaches said first lower wiring section, said second interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said second lower wiring section; a first upper wiring section, connected with said first conductor, covering the upper surface of said second interlayer insulating region, said first upper wiring section having an upper surface and a side surface; a third insulating film covering only the upper surface and the side-wall surface of said first upper wiring section but not extending beyond the side-wall surface of said first upper wiring section onto the upper surface of said second interlayer insulating film; a second conductor, embedded in the second contact hole, for connecting with said first lower wiring section; and a second upper wiring section covering said second conductor, the upper surface of said second interlayer insulating region, and said third insulating film, said second upper wiring section in direct contact with the upper surface of said second interlayer insulating film, whereby said second upper wiring section overlies said first upper wiring section with said second upper wiring section isolated from said first upper wiring section by said third insulating film.

Claim 22

A semiconductor device as claimed in claim 17, wherein said first upper wiring section comprises a polysilicon film which consists essentially of polysilicon, said polysilicon film having an upper surface, and a high melting-point metal silicide film formed on the upper surface of said polysilicon film.

Claim 23

A semiconductor device as claimed in claim 18, wherein said high melting-point metal silicide film consists of a tungsten silicide film.

Claim 24

In a semiconductor memory device comprising a plurality of memory cells each of which includes a switching transistor and a capacitor section having a storage lower electrode, each of said memory cells comprising: a semiconductor substrate having a principal surface; a thick field oxide film which is formed on the principal surface of said semiconductor substrate and which defines an element forming region; a gate insulating film formed on the element forming region; a gate electrode selectively coating said gate insulating film; first and second impurity regions formed under the principal surface of said semiconductor substrate in the element forming region except for said gate electrode, said first and said second impurity regions serving as source/drain regions, thereby forming said switching transistor which comprises said gate electrode and said source/drain regions; an interlayer insulating region covering said switching transistor, said interlayer insulating region having first and second contact holes which reach the first and the second conductive sections, respectively, said interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first impurity region; a first conductive region, connected with said first conductor, covering the upper surface of said interlayer insulating region, said first conductive region being composed of a bit line, said first conductive region having an upper surface and a side surface; an inter-region insulating film covering only the upper surface and the side-wall surface of said first conductive region, but not extending beyond the side-wall surface of said first conductive region onto the upper surface of said interlayer insulating region; a second conductor, embedded in the second contact hole, for connecting with said second impurity region; and a second conductive region covering said second conductor, the upper surface of said interlayer insulating region, and said inter-region insulating film, said second conductive region overlying said first conductive region and in direct contact with the upper surface of said interlayer insulating region with said second conductive region isolated from said first conductive region by said inter-region insulating film, whereby said second conductive region serves as said storage lower electrode.

Claim 25

In a semiconductor memory device comprising a plurality of memory cells each of which includes a switching transistor and a capacitor section having a storage lower electrode, each of said memory cells comprising: a semiconductor substrate having a principal surface; a thick field oxide film which is formed on the principal surface of said semiconductor substrate and which defines an element forming region; a gate insulating film formed on the element forming region; a gate electrode selectively coating said gate insulating film; first and second impurity regions formed under the principal surface of said semiconductor substrate in the element forming region except for said gate electrode, said first and said second impurity regions serving as source/drain regions, thereby forming said switching transistor which comprises said gate electrode and said source/drain regions; an interlayer insulating region covering said switching transistor, said interlayer insulating region having first and second contact holes which reach the first and the second conductive sections, respectively, said interlayer insulating region having an upper surface; a first conductor, embedded in the first contact hole, for connecting with said first impurity region; a first conductive region, connected with said first conductor, covering the upper surface of said interlayer insulating region, said first conductive region being composed of a bit line, said first conductive region having an upper surface and a side surface; an inter-region insulating film covering only the upper surface and the side-wall surface of said first conductive region, but not extending beyond the side-wall surface of said first conductive region onto the upper surface of said interlayer insulating region; a second conductor, embedded in the second contact hole, for connecting with said second impurity region; and a second conductive region covering said second conductor, the upper surface of said interlayer insulating region, and said inter-region insulating film, said second conductive region overlying said first conductive region and in direct contact with the upper surface of said interlayer insulating region with said second conductive region isolated from said first conductive region by said inter-region insulating film, whereby said second conductive region serves as said storage lower electrode.

Claim 26

A semiconductor memory device as claimed in claim 20, wherein each of said first and said second conductors consists essentially of polysilicon.

Claim 27

A semiconductor memory device as claimed in claim 20, wherein said first conductive region comprises a polysilicon film which consists essentially of polysilicon, said polysilicon film having an upper surface, and a high melting-point metal silicide film formed on the upper surface of said polysilicon film.

Claim 28

A semiconductor memory device as claimed in claim 20, wherein each of said memory cells further comprises a capacitor dielectric film coating said storage lower electrode and a storage upper electrode covering said capacitor dielectric film, thereby resulting in said capacitor section.

Claim 29

A semiconductor memory device as claimed in claim 22, wherein said high melting-point metal silicide film consists of a tungsten silicide film.