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JPS6243149A Expired / Lapsed JP ⏱️ 0.0 years remaining

Forming method of multilayer wiring

Assignee: Sony Corp
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Filing: 1985-08-21
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Granted: —
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Expires: 2005-08-21
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Abstract

Abstract PURPOSE:To suppress the yield of hillocks and remnants, which deteriorate the characteristics of elements and the reliability of wirings, by covering the surface of a lower layer wiring with a nitride film, and forming side walls. CONSTITUTION:In forming processed, the surface of a lower layer wiring 11 using a low melting point metal or a low melting point metal alloy is covered with a nitride film 12. Thus, hillocks, which are liable to yield on the surface of the wiring, can be prevented. The nitride film (hillock preventing film) serves the role of a stopper so that the lower wiring layer 11 and an oxide film 16 are not etched when an insulating film 13 is etched in order to form side walls 14. The formed side walls 14 alleviate the step on the lower layer wiring 11 and change the step into the gentle inclination. Therefore, an interlayer insulating film (PSG) 17 to be formed thereon can be formed uniformly. Thus, excellent coating property is obtained. An upper layer wiring 19 is formed, and the upper layer wiring film is etched. Since, e.g., a step part A has the gentle inclination owing to the lower side walls, the thickness of the wiring film becomes uniform, and the remnant of the wiring film is hard to occur even in this case of the etching.

Inventors

  • 👤 Masataka Shinguu
  • 👤 新宮 正孝
  • 👤 Saburo Tsukada
  • 👤 塚田 三郎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 22:50
CPC Classifications
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