Output buffer circuit having gate voltage control circuit of gate current controlling transistor connected to output transistor

Claim 2

An output buffer circuit comprising: a first output transistor which is provided between said output terminal and a first power supply terminal and receives an input signal at a gate thereof through a gate current controlling transistor; and a voltage control circuit which supplies the gate of said gate current controlling transistor with a first voltage which causes said gate current controlling transistor to have a first current driving capability for a predetermined time in response to a change of said input signal to render said first output transistor conductive and generates a second voltage which causes said gate current controlling transistor to have a second current driving capability that is higher than said first current driving capability after elapse of said predetermined time.

Claim 3

An output buffer circuit as set forth in claim 1, wherein said first output transistor is a P-channel type transistor and said output buffer circuit further comprises a second output transistor which is an N-channel type zero threshold transistor and said second power supply terminal is a ground terminal.

Claim 4

An output buffer circuit as set forth in claim 1, wherein said voltage control circuit comprises: a gate voltage control signal generation circuit which generates a control signal of a first logical level for said predetermined time and generates a control signal of a second logical level after elapse of said predetermined time in response to a change in said input signal when said second output transistor is turned from an OFF state to an ON state; and a gate voltage generating circuit which supplies the gate of said gate current controlling transistor with said first voltage when said control signal is at the first logical level and supplies the gate of said gate current controlling transistor with said second voltage when said control signal is at the second logical level.

Claim 5

An output buffer circuit as set forth in claim 3, wherein said gate voltage signal generation circuit comprises: a delay circuit for delaying a signal which is obtained in accordance with a change in said input signal by said predetermined time; and a logical circuit which receives an output from said delay circuit and said input signal and generates a control signal of the first logical level for said predetermined time and generates a control signal of the second logical level after the elapse of said predetermined time.

Claim 6

An output buffer circuit as set forth in claim 1, wherein said voltage control circuit generates said second voltage value as the gate voltage of said gate current controlling transistor in response to a change in said input signal when said first output transistor is turned from the OFF state to the ON state.

Claim 7

An output buffer circuit comprising: a P-channel type output transistor which is provided between a first power supply terminal and an output terminal and receives an input signal at a gate thereof; an N-channel type output transistor which is provided between said output terminal and a second power supply and has a gate; a means for supplying said input signal to the gate of said N-channel type output transistor through a gate current controlling transistor; and a voltage control generation circuit which generates as a gate voltage of said gate current controlling transistor a first voltage value which is smaller than a value of a power supply voltage and enables conduction of said gate current controlling transistor with a predetermined resistance value for a predetermined time in response to a change of the level of said input signal from a low level to a high level and further generates a second voltage value which is higher than said first voltage value after elapse of said predetermined time.

Claim 8

An output buffer circuit comprising: a P-channel type output transistor which is provided between a first power supply terminal and an output terminal and receives an input signal at a gate thereof; an N-channel type output transistor which is provided between said output terminal and a second power supply and has a gate; a means for supplying said input signal to the gate of said N-channel type output transistor through a gate current controlling transistor; and a voltage control generation circuit which generates as a gate voltage of said gate current controlling transistor a first voltage value which is smaller than a value of a power supply voltage and enables conduction of said gate current controlling transistor with a predetermined resistance value for a predetermined time in response to a change of the level of said input signal from a low level to a high level and further generates a second voltage value which is higher than said first voltage value after elapse of said predetermined time.

Claim 9

An output buffer circuit as set forth in claim 6, wherein said voltage control circuit comprises: a gate voltage control signal generation circuit which generates a control signal of a first logical level for said predetermined time in response to a change of the level of said input signal from the low level to the high level and further generates a control signal of a second logical level after elapse of said predetermined time; and a gate voltage generation circuit which supplies the gate of said gate current controlling transistor with said first voltage value when said control signal is at the first logical level and supplies the gate of said gate current controlling transistor with said second voltage value when said control signal is at the second logical level.

Claim 10

An output buffer circuit comprising: an NOR circuit for receiving an input signal and a control signal; a first inverter for receiving an output from said NOR circuit; a first P-type MOS transistor whose source is connected to a power supply; a first N-type MOS transistor which has a source grounded and a drain connected to a drain of said first P-type MOS transistor and outputs an output signal; a first transfer gate which includes by a second P-type MOS transistor whose source is connected to an output of said first inverter and whose drain is connected to a gate of said first P-type MOS transistor and a second N-type MOS transistor; a NAND circuit for receiving said input signal and an inverted signal obtained from said control signal; a second inverter for receiving an output from said NAND circuit; a second transfer gate which includes a third N-type MOS transistor having a source connected to an output of said second inverter and a drain connected to a gate of said first N-type MOS transistor; and a voltage control circuit which receives said control signal, an output from said NOR circuit and an output from said NAND circuit, and which has a first output connected to a gate of said second P-type MOS transistor, a second output connected to a gate of said third N-type MOS transistor and a third output connected to a gate of said second N-type MOS transistor, thereby gradually changing an output to a gate of said first or second gate transfer from an intermediate potential equal to or lower than the power supply potential to the power supply potential during a time period in which the potential of said output signal is turned to the power supply potential or a ground potential.

Claim 11

An output buffer circuit comprising: an NOR circuit for receiving an input signal and a control signal; a first inverter for receiving an output from said NOR circuit; a first P-type MOS transistor whose source is connected to a power supply; a first N-type MOS transistor which has a source grounded and a drain connected to a drain of said first P-type MOS transistor and outputs an output signal; a first transfer gate which includes by a second P-type MOS transistor whose source is connected to an output of said first inverter and whose drain is connected to a gate of said first P-type MOS transistor and a second N-type MOS transistor; a NAND circuit for receiving said input signal and an inverted signal obtained from said control signal; a second inverter for receiving an output from said NAND circuit; a second transfer gate which includes a third N-type MOS transistor having a source connected to an output of said second inverter and a drain connected to a gate of said first N-type MOS transistor; and a voltage control circuit which receives said control signal, an output from said NOR circuit and an output from said NAND circuit, and which has a first output connected to a gate of said second P-type MOS transistor, a second output connected to a gate of said third N-type MOS transistor and a third output connected to a gate of said second N-type MOS transistor, thereby gradually changing an output to a gate of said first or second gate transfer from an intermediate potential equal to or lower than the power supply potential to the power supply potential during a time period in which the potential of said output signal is turned to the power supply potential or a ground potential.

Claim 12

An output buffer circuit as set forth in claim 8, wherein said second N-type MOS transistor in said first transfer gate and said third N-type MOS transfer in said second transfer gate are N-type zero threshold transistors.