US5551050A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method using synchronized processors to perform real time internal monitoring of a data processing device
Assignee: Texas Instruments Inc
•
Filing: 1994-11-14
•
Granted: 1996-08-27
•
Expires: 2014-11-14
Abstract
Abstract A system and method for real time internal bus monitoring of a data processing device is disclosed. A plurality of processors having address outputs, data lines, and clocks are connected to a synchronizing circuit to lock the clocks of the processors in phase. A memory is connected to all of the data lines in common and is connected to the address outputs of fewer than all of the processors. Emulation circuitry is connected to the address outputs of a processor instead of said memory. The method discloses synchronizing the processors by locking the clocks in phase. Then accessing the system memory by addressing it with the address output of only one of the processors. And finally, monitoring at least one of the other processors via its address output.
Inventors
- 👤 Peter N. Ehlig
- 👤 Gary L. Swoboda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
194 words
A method of operating a data processing system including a plurality of processors each having an address output, data lines, and a clock, comprising the steps of: synchronizing the plurality of processors by locking the clock of each of said plurality of processors in phase; accessing data from a system memory connected to the data lines of the plurality of processors by addressing the data in the system memory with the address output of a first of said plurality of processors and providing the addressed data to each of said processors; monitoring internal operations of said plurality of processors via the address output of a second of said plurality of processors; operating the plurality of processors redundantly so that each processor arrives at an answer by calculating identical data from said data lines; and supplying the answer of the second of said plurality of processors and the answer of a third of said plurality of processors through their address outputs which are not connected to the system memory to a comparison circuit, and voting on the answers supplied through their address outputs to create an error flag when a discrepancy occurs between the answers.
Claim 2
Independent Claim
194 words
A method of operating a data processing system including a plurality of processors each having an address output, data lines, and a clock, comprising the steps of: synchronizing the plurality of processors by locking the clock of each of said plurality of processors in phase; accessing data from a system memory connected to the data lines of the plurality of processors by addressing the data in the system memory with the address output of a first of said plurality of processors and providing the addressed data to each of said processors; monitoring internal operations of said plurality of processors via the address output of a second of said plurality of processors; operating the plurality of processors redundantly so that each processor arrives at an answer by calculating identical data from said data lines; and supplying the answer of the second of said plurality of processors and the answer of a third of said plurality of processors through their address outputs which are not connected to the system memory to a comparison circuit, and voting on the answers supplied through their address outputs to create an error flag when a discrepancy occurs between the answers.
Claim 3
Dependent Claim
285 words
A data processing system configured to operate in lock step such that one processor sends out addresses for reading data while other processors use their address outputs for transmitting internal information, comprising: a system memory; a system data bus connected to the system memory; a clock synchronization circuit; a first processor having a clock, an address output, and a data input/output, the clock connected to the clock synchronization circuit, the address output connected to the system memory; and the data input/output connected through the system data bus to the system memory; a second processor having a clock, an address output, a data input/output, and an internal status bus, the clock connected to the clock synchronization circuit, the address output connected to a first monitor circuit, the data input/output connected through the system data bus to the system memory, and the internal status bus connected to the address output; a third processor having a clock, an address output, a data input/output, and an internal data bus, the clock connected to the clock synchronization circuit, the address output connected to a second monitor circuit, the data input/output connected through the system data bus to the system memory, and the internal data bus connected to the address output; and as the clock synchronization circuit synchronizes the clock of the first, the second, and third processor in phase, the processors operate in lock step whereby the first processor sends out addresses for reading data from the system memory through its address output while the second processor sends out internal status data through its address output to the first monitor circuit and the third processor sends out internal data bus data through its address output to the second monitor circuit.
Claim 4
Dependent Claim
285 words
A data processing system configured to operate in lock step such that one processor sends out addresses for reading data while other processors use their address outputs for transmitting internal information, comprising: a system memory; a system data bus connected to the system memory; a clock synchronization circuit; a first processor having a clock, an address output, and a data input/output, the clock connected to the clock synchronization circuit, the address output connected to the system memory; and the data input/output connected through the system data bus to the system memory; a second processor having a clock, an address output, a data input/output, and an internal status bus, the clock connected to the clock synchronization circuit, the address output connected to a first monitor circuit, the data input/output connected through the system data bus to the system memory, and the internal status bus connected to the address output; a third processor having a clock, an address output, a data input/output, and an internal data bus, the clock connected to the clock synchronization circuit, the address output connected to a second monitor circuit, the data input/output connected through the system data bus to the system memory, and the internal data bus connected to the address output; and as the clock synchronization circuit synchronizes the clock of the first, the second, and third processor in phase, the processors operate in lock step whereby the first processor sends out addresses for reading data from the system memory through its address output while the second processor sends out internal status data through its address output to the first monitor circuit and the third processor sends out internal data bus data through its address output to the second monitor circuit.
References Cited (Backward Citations)
US4358823A
Cited
US4141066A
Cited
US4251873A
Cited
US4435759A
Cited
US4571677A
Cited
US4581701A
Cited
US4628445A
Cited
US5115502A
Cited
US4674089A
Cited
US4941087A
Cited
US5132971A
Cited
US5005174A
Cited
US5101498A
Cited
US5109333A
Cited
US5054026A
Cited
US5146589A
Cited
US5008805A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |