In an interactive network board, a method and apparatus for preventing inadvertent loading of a programmable read only memory

Claim 5

An apparatus according to claim 2, wherein said latch is responsive to a write to the first predetermined address.

Claim 6

An apparatus according to claim 2, wherein said decoder is responsive to a read from the second predetermined address.

Claim 7

An apparatus according to claim 2, wherein said processor, after loading the ROM firmware image into said EPROM, outputs a second predetermined bit pattern, which is different from the first predetermined bit pattern, to the first predetermined address and which again accesses the second predetermined address.

Claim 8

An apparatus according to claim 2, wherein the flip flop powers up such that said switch is prevented from providing the load enable signal to the load enable input of said EPROM.

Claim 9

An apparatus according to claim 2, wherein, upon power-up, said latch is set such that the flip flop is not pre-loaded.

Claim 10

An apparatus according to claim 2, wherein said means responsive is comprised of a DC to DC converter and further includes means for discharge of the load enable signal.

Claim 11

An apparatus according to claim 2, further comprising an NVRAM for non-volatively storing data, wherein the latch latches read and write data for the NVRAM.

Claim 12

An apparatus according to claim 9, wherein said latch latches a read/write control bit, a clock bit, and a data bit for the NVRAM.

Claim 13

An apparatus according to claim 10, wherein said latch utilizes a further bit to activate the means responsive.

Claim 14

An apparatus according to claim 2, wherein said EPROM is comprised by a flash EPROM.

Claim 15

An apparatus according to claim 2, wherein said apparatus is disposed on an interactive network board.

Claim 16

An apparatus according to claim 2, wherein the apparatus is disposed on an interactive network board coupled to a printer.

Claim 17

An interactive network board having an EPROM load protection circuit, comprising: a bi-directional interface disposed on the board; a LAN interface disposed on the board; a test interface disposed on the board; a RAM, disposed on the board, for storing a ROM firmware image received over the LAN interface; an EPROM, disposed on the board and responsive to an erase command and a load command, for storing the ROM firmware image, said EPROM having a load enable input for receiving a load enable signal, the load enable signal for permitting programming of said EPROM; a switch for switchably providing the load enable signal to the load enable input of said EPROM; and a processor, disposed on the board, for processing executable files from the ROM firmware image stored in the EPROM, and wherein said processor is responsive to a LAN command from a remote LAN device to store a new ROM firmware image in said RAM, to load the new ROM firmware image from said RAM into said EPROM, and to reboot the interactive network board from the new ROM firmware image in said EPROM, said processor causing said switch to close by (1) issuing a write command to a first address in order to generate a first signal for closing said switch, and (2) issuing a read command to a second address in order to generate a second signal for clocking the first signal to the switch in order to close the switch and to permit a load enable signal to be provided to the load enable input of said EPROM, the load enable signal for permitting programming of the EPROM by loading the ROM firmware image from said RAM into said EPROM; wherein the load enable input of said EPROM is substantially grounded so as to prevent inadvertent programming of said EPROM whenever the load enable signal is prevented from being provided to the load enable input of said EPROM.

Claim 18

An interactive network board having an EPROM load protection circuit, comprising: a bi-directional interface disposed on the board; a LAN interface disposed on the board; a test interface disposed on the board; a RAM, disposed on the board, for storing a ROM firmware image received over the LAN interface; an EPROM, disposed on the board and responsive to an erase command and a load command, for storing the ROM firmware image, said EPROM having a load enable input for receiving a load enable signal, the load enable signal for permitting programming of said EPROM; a switch for switchably providing the load enable signal to the load enable input of said EPROM; and a processor, disposed on the board, for processing executable files from the ROM firmware image stored in the EPROM, and wherein said processor is responsive to a LAN command from a remote LAN device to store a new ROM firmware image in said RAM, to load the new ROM firmware image from said RAM into said EPROM, and to reboot the interactive network board from the new ROM firmware image in said EPROM, said processor causing said switch to close by (1) issuing a write command to a first address in order to generate a first signal for closing said switch, and (2) issuing a read command to a second address in order to generate a second signal for clocking the first signal to the switch in order to close the switch and to permit a load enable signal to be provided to the load enable input of said EPROM, the load enable signal for permitting programming of the EPROM by loading the ROM firmware image from said RAM into said EPROM; wherein the load enable input of said EPROM is substantially grounded so as to prevent inadvertent programming of said EPROM whenever the load enable signal is prevented from being provided to the load enable input of said EPROM.

Claim 19

An interactive network board according to claim 15, wherein the interactive network board is coupled to a printer.

Claim 20

An interactive network board according to claim 15, wherein the RAM is a dynamic RAM.

Claim 21

An interactive network board according to claim 15, wherein said EPROM comprises a flash EPROM.

Claim 22

An interactive network board having a LAN interface, a bi-directional interface, and a test interface for loading a ROM firmware image into an EPROM disposed on the board, comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting loading of a ROM firmware image into said EPROM; a flip flop for controlling switching actuation of said switch; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus, said latch pre-loading the flip flop with the latched at least one bit; means responsive to said latch latching the at least one bit for providing the load enable signal to said switch; a decoder responsive to a second predetermined address on said address bus for clocking said flip flop; and a processor for outputting the predetermined bit pattern to the first address and for accessing the second predetermined address so as to close said switch to permit the load enable signal to be provided to the load enable input of said EPROM, for erasing said EPROM, and for loading the ROM firmware image into said EPROM, wherein said processor is responsive to a LAN downloaded command to load the ROM firmware image into a RAM and is responsive to a LAN downloaded command to load said EPROM with the ROM firmware image stored in the RAM; and wherein the load enable input is substantially grounded whenever said switch is open so as to prevent loading of a ROM firmware image into said EPROM.

Claim 23

An interactive network board having a LAN interface, a bi-directional interface, and a test interface for loading a ROM firmware image into an EPROM disposed on the board, comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting loading of a ROM firmware image into said EPROM; a flip flop for controlling switching actuation of said switch; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus, said latch pre-loading the flip flop with the latched at least one bit; means responsive to said latch latching the at least one bit for providing the load enable signal to said switch; a decoder responsive to a second predetermined address on said address bus for clocking said flip flop; and a processor for outputting the predetermined bit pattern to the first address and for accessing the second predetermined address so as to close said switch to permit the load enable signal to be provided to the load enable input of said EPROM, for erasing said EPROM, and for loading the ROM firmware image into said EPROM, wherein said processor is responsive to a LAN downloaded command to load the ROM firmware image into a RAM and is responsive to a LAN downloaded command to load said EPROM with the ROM firmware image stored in the RAM; and wherein the load enable input is substantially grounded whenever said switch is open so as to prevent loading of a ROM firmware image into said EPROM.

Claim 24

An apparatus according to claim 19, wherein said EPROM comprises a flash EPROM.

Claim 25

An interactive network board according to claim 19, wherein the interactive network board is coupled to a printer.

Claim 28

An apparatus according to claim 20, wherein the apparatus is disposed on an interactive network board coupled to a printer.

Claim 29

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting a ROM firmware image to be loaded into said EPROM, the load enable input of the EPROM being substantially grounded whenever said switch is open; a flip flop for controlling switching actuation of said switch; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus, said latch pre-loading the flip flop with the latched bit; means responsive to said latch latching the at least one bit for providing the load enable signal to said switch; a decoder responsive to a second predetermined address on said address bus for clocking said flip flop; and a processor (1) for outputting a first predetermined bit pattern to the first predetermined address and for accessing the second predetermined address so as to close said switch to permit the load enable signal to be provided to the load enable input of said EPROM, for erasing said EPROM, and for loading the ROM firmware image into said EPROM, and (2) for executing a print server program to transmit the print data received from the LAN to said print engine.

Claim 30

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting a ROM firmware image to be loaded into said EPROM, the load enable input of the EPROM being substantially grounded whenever said switch is open; a flip flop for controlling switching actuation of said switch; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus, said latch pre-loading the flip flop with the latched bit; means responsive to said latch latching the at least one bit for providing the load enable signal to said switch; a decoder responsive to a second predetermined address on said address bus for clocking said flip flop; and a processor (1) for outputting a first predetermined bit pattern to the first predetermined address and for accessing the second predetermined address so as to close said switch to permit the load enable signal to be provided to the load enable input of said EPROM, for erasing said EPROM, and for loading the ROM firmware image into said EPROM, and (2) for executing a print server program to transmit the print data received from the LAN to said print engine.

Claim 31

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: a bi-directional interface disposed on the board; a LAN interface disposed on the board; a test interface disposed on the board; a RAM, disposed on the board, for storing a ROM firmware image received over the LAN interface; an EPROM, disposed on the board and responsive to an erase command and a load command, for storing the ROM firmware image, said EPROM having a load enable input for receiving a load enable signal, the load enable signal for permitting programming of said EPROM; a switch for switchably providing the load enable signal to the load enable input of said EPROM; and a processor, disposed on the board, for processing executable files from the ROM firmware image stored in the EPROM and for executing a print server program to transmit the print data to said print engine, and wherein said processor is responsive to a LAN command from a remote LAN device to store a new ROM firmware image in said RAM, to load the new ROM firmware image from said RAM into said EPROM, and to reboot the interactive network board from the new ROM firmware image in said EPROM, said processor causing said switch to close by (1) issuing a write command to a first address in order to generate a first signal for closing said switch, and (2) issuing a read command to a second address in order to generate a second signal for clocking the first signal to the switch in order to close the switch and to permit a load enable signal to be provided to the load enable input of said EPROM, the load enable signal for permitting programming of the EPROM by loading the ROM firmware image from said RAM into said EPROM; wherein the load enable input of said EPROM is substantially grounded so as to prevent inadvertent programming of said EPROM whenever the load enable signal is prevented from being provided to the load enable input of said EPROM.

Claim 32

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: a bi-directional interface disposed on the board; a LAN interface disposed on the board; a test interface disposed on the board; a RAM, disposed on the board, for storing a ROM firmware image received over the LAN interface; an EPROM, disposed on the board and responsive to an erase command and a load command, for storing the ROM firmware image, said EPROM having a load enable input for receiving a load enable signal, the load enable signal for permitting programming of said EPROM; a switch for switchably providing the load enable signal to the load enable input of said EPROM; and a processor, disposed on the board, for processing executable files from the ROM firmware image stored in the EPROM and for executing a print server program to transmit the print data to said print engine, and wherein said processor is responsive to a LAN command from a remote LAN device to store a new ROM firmware image in said RAM, to load the new ROM firmware image from said RAM into said EPROM, and to reboot the interactive network board from the new ROM firmware image in said EPROM, said processor causing said switch to close by (1) issuing a write command to a first address in order to generate a first signal for closing said switch, and (2) issuing a read command to a second address in order to generate a second signal for clocking the first signal to the switch in order to close the switch and to permit a load enable signal to be provided to the load enable input of said EPROM, the load enable signal for permitting programming of the EPROM by loading the ROM firmware image from said RAM into said EPROM; wherein the load enable input of said EPROM is substantially grounded so as to prevent inadvertent programming of said EPROM whenever the load enable signal is prevented from being provided to the load enable input of said EPROM.

Claim 33

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting loading of a ROM firmware image into said EPROM; a flip flop for controlling switching actuation of said switch; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus, said latch pre-loading the flip flop with the latched at least one bit; means responsive to said latch latching the at least one bit for providing the load enable signal to said switch; a decoder responsive to a second predetermined address on said address bus for clocking said flip flop; and a processor (1) for executing a print server program to transmit the print data received from the LAN to said print engine, and (2) for outputting the predetermined bit pattern to the first address and for accessing the second predetermined address so as to close said switch to permit the load enable signal to be provided to the load enable input of said EPROM, for erasing said EPROM, and for loading the ROM firmware image into said EPROM, wherein said processor is responsive to a LAN downloaded command to load the ROM firmware image into a RAM and is responsive to a LAN downloaded command to load said EPROM with the ROM firmware image stored in the RAM; and wherein the load enable input is substantially grounded whenever said switch is open so as to prevent loading of a ROM firmware image into said EPROM.

Claim 34

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting loading of a ROM firmware image into said EPROM; a flip flop for controlling switching actuation of said switch; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus, said latch pre-loading the flip flop with the latched at least one bit; means responsive to said latch latching the at least one bit for providing the load enable signal to said switch; a decoder responsive to a second predetermined address on said address bus for clocking said flip flop; and a processor (1) for executing a print server program to transmit the print data received from the LAN to said print engine, and (2) for outputting the predetermined bit pattern to the first address and for accessing the second predetermined address so as to close said switch to permit the load enable signal to be provided to the load enable input of said EPROM, for erasing said EPROM, and for loading the ROM firmware image into said EPROM, wherein said processor is responsive to a LAN downloaded command to load the ROM firmware image into a RAM and is responsive to a LAN downloaded command to load said EPROM with the ROM firmware image stored in the RAM; and wherein the load enable input is substantially grounded whenever said switch is open so as to prevent loading of a ROM firmware image into said EPROM.

Claim 35

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting a ROM firmware image to be loaded into said EPROM; a flip flop for controlling switching actuation of said switch with an output thereof, said flip flop having an output terminal, a data terminal and a trigger terminal for clocking a signal at the data terminal to the output terminal; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus so as to generate a first signal, the first signal being provided to the data terminal of said flip flop; a power generator for generating the load enable signal and for providing the load enable signal to said switch, the load enable signal being generated in response to the first signal from said latch; a decoder responsive to a second predetermined address on said address bus for generating a second signal, the second signal being provided to the trigger terminal of said flip flop so as to clock a signal at the data terminal to the output terminal; and a processor (1) for executing a print server program to transmit the print data received from the LAN to said print engine, and (2) for outputting a first predetermined bit pattern to the data bus to the first predetermined address so as to cause said latch to provide the first signal to the data terminal of said flip flop and to said power generator, and for accessing the second predetermined address so as to activate said decoder to generate the second signal and to provide the second signal to the trigger terminal of said flip flop; wherein, when the second signal is applied to the trigger terminal of said flip flop, said flip flop transmits the first signal through to the output terminal, the transferred first signal controlling actuation of said switch so as to permit the load enable signal to be provided from said power generator to the load enable input of said EPROM.

Claim 36

A printer connected to a local area network (LAN), comprising: a print engine which forms printed images from print data received from the LAN; and an interactive network board, interfaced to said print engine and to the LAN, for receiving the print data from the LAN and for providing the print data to said print engine, said interactive network board comprising: an address bus; a data bus; an EPROM connected to said address bus and to said data bus, said EPROM including a load enable input; a switch for switchably providing a load enable signal to the load enable input of said EPROM, the load enable signal for permitting a ROM firmware image to be loaded into said EPROM; a flip flop for controlling switching actuation of said switch with an output thereof, said flip flop having an output terminal, a data terminal and a trigger terminal for clocking a signal at the data terminal to the output terminal; a latch responsive to a first predetermined address on the address bus for latching at least one bit from the data bus so as to generate a first signal, the first signal being provided to the data terminal of said flip flop; a power generator for generating the load enable signal and for providing the load enable signal to said switch, the load enable signal being generated in response to the first signal from said latch; a decoder responsive to a second predetermined address on said address bus for generating a second signal, the second signal being provided to the trigger terminal of said flip flop so as to clock a signal at the data terminal to the output terminal; and a processor (1) for executing a print server program to transmit the print data received from the LAN to said print engine, and (2) for outputting a first predetermined bit pattern to the data bus to the first predetermined address so as to cause said latch to provide the first signal to the data terminal of said flip flop and to said power generator, and for accessing the second predetermined address so as to activate said decoder to generate the second signal and to provide the second signal to the trigger terminal of said flip flop; wherein, when the second signal is applied to the trigger terminal of said flip flop, said flip flop transmits the first signal through to the output terminal, the transferred first signal controlling actuation of said switch so as to permit the load enable signal to be provided from said power generator to the load enable input of said EPROM.