Patent US5550075A successfully refreshed from Google Patents.
US5550075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ion implanted programmable cell for read only memory applications
Assignee: United Microelectronics Corp
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Filing: 1995-01-19
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Granted: 1996-08-27
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Expires: 2015-01-19
Abstract
Abstract A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.
Inventors
- 👤 Chen-Chung Hsu
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:58
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/10; Y; Y10; Y10S; Y10S257/00; Y10S257/91; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
282 words
A method of fabricating a read only memory, (ROM), cell on a semiconductor substrate, having a first conductivity, comprising the steps of: forming a field oxide pattern on regions of said substrate, while leaving silicon unoxidized on remaining regions of said substrate; photolithography to expose portions of said unoxidized silicon; ion implanting second conductivity imparting dopants into said exposed portions of said unoxidized silicon; growing a first oxide layer on said exposed portions of said ion implanted silicon; growing a second oxide layer on non-implanted silicon; growing a second oxide layer on non-implanted silicon, said first oxide layer having a thickness greater than a thickness of said second oxide layer; photolithography to expose a specific area of said first oxide layer grown on said ion implanted silicon to program said ROM cell; removal of said first oxide layer, from said specific area of said ion implanted silicon; depositing a polysilicon layer on said field oxide, on said second oxide layer grown on said non-ion implanted silicon, on said first oxide layer grown on said ion implanted silicon, and on said ion implanted silicon in said specific area where said first oxide layer has been removed; ion implanting a first conductivity imparting dopant into said polysilicon layer; annealing to drive said first conductivity imparting dopant, into said specific area of said ion implanted silicon, where said first oxide layer has been removed; and patterning to form polysilicon gate structure on said field oxide, on said second oxide layer grown on said non-ion implanted silicon, on said first oxide layer grown on said ion implanted silicon, and on said specific area of said ion implanted silicon, where said first oxide layer has been removed.
Claim 2
Independent Claim
282 words
A method of fabricating a read only memory, (ROM), cell on a semiconductor substrate, having a first conductivity, comprising the steps of: forming a field oxide pattern on regions of said substrate, while leaving silicon unoxidized on remaining regions of said substrate; photolithography to expose portions of said unoxidized silicon; ion implanting second conductivity imparting dopants into said exposed portions of said unoxidized silicon; growing a first oxide layer on said exposed portions of said ion implanted silicon; growing a second oxide layer on non-implanted silicon; growing a second oxide layer on non-implanted silicon, said first oxide layer having a thickness greater than a thickness of said second oxide layer; photolithography to expose a specific area of said first oxide layer grown on said ion implanted silicon to program said ROM cell; removal of said first oxide layer, from said specific area of said ion implanted silicon; depositing a polysilicon layer on said field oxide, on said second oxide layer grown on said non-ion implanted silicon, on said first oxide layer grown on said ion implanted silicon, and on said ion implanted silicon in said specific area where said first oxide layer has been removed; ion implanting a first conductivity imparting dopant into said polysilicon layer; annealing to drive said first conductivity imparting dopant, into said specific area of said ion implanted silicon, where said first oxide layer has been removed; and patterning to form polysilicon gate structure on said field oxide, on said second oxide layer grown on said non-ion implanted silicon, on said first oxide layer grown on said ion implanted silicon, and on said specific area of said ion implanted silicon, where said first oxide layer has been removed.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein said field oxide is grown to a thickness between about 4000 to 6000 Angstroms.
Claim 4
Dependent Claim
54 words
The method of claim 1, wherein said second conductivity imparting dopants are arsenic, ion implanted at an energy between about 50 to 100 Kev., at a dose between about 1E14 to 1E16 atoms/cm2, and phosphorous, ion implanted at an energy between 30 to 60 Kev., at a dose between about 1E14 to 1E16 atoms/cm2.
Claim 5
Dependent Claim
36 words
The method of claim 1, wherein said first oxide layer, grown on said ion implanted silicon, is grown at a temperature between about 850° to 950° C., to a thickness between about 800 to 2000 Angstroms.
Claim 6
Dependent Claim
36 words
The method of claim 1, wherein said second oxide layer, grown on said non-ion implanted silicon, is grown at a temperature between about 850° to 950° C., to a thickness between about 400 to 1000 Angstroms.
Claim 7
Dependent Claim
22 words
The method of claim 1, wherein said first oxide layer, grown on said ion implanted silicon, is removed using buffered hydrofluoric acid.
Claim 8
Dependent Claim
20 words
The method of claim 1, wherein said polysilicon layer is deposited to a thickness between about 1200 to 1800 Angstroms.
Claim 9
Dependent Claim
33 words
The method of claim 1, wherein said first conductivity imparting dopant is boron, ion implanted at an energy between about 30 to 60 Kev., at a dose between about 1E14 to 1E16 atoms/cm2.
Claim 10
Dependent Claim
28 words
The method of claim 1, wherein said anneal is performed at a temperature between about 850° to 950° C., for a time between about 30 to 60 min.
Claim 11
Independent Claim
280 words
A method of fabricating a read only memory, (ROM), cell on a semiconductor substrate, having a first conductivity, comprising the steps of: forming a field oxide pattern on regions of said substrate, while leaving silicon unoxidized on remaining regions of said substrate photolithography to expose portions of said unoxidized silicon; ion implanting second conductivity imparting dopants into said exposed portions of said unoxidized silicon, to form buried bit line regions; growing a first oxide layer on said buried bit line regions; growing a second oxide layer on non-implanted silicon regions, said first oxide layer having a thickness greater than a thickness of said second oxide layer; photolithography to expose a specific area of said first oxide layer, grown on said buried bit line regions to program said ROM cell; removal of said first oxide layer, from said specific area of said buried bit line regions; depositing a polysilicon layer on said field oxide, on said second oxide layer on said non-ion implanted silicon, on said first oxide layer grown on said buried bit line regions, and on said buried bit line regions, in specific area where said first oxide layer has been removed; ion implanting a first conductivity imparting dopant into said polysilicon layer; annealing to drive, said first conductivity imparting dopant, into said specific area of said buried bit line regions, where said first oxide layer has been removed, to form a diode; and patterning said polysilicon layer to form a word line on said field oxide, on said second oxide layer on said non-ion implanted silicon, on said first oxide layer on said buried bit line regions, and on said diode, formed in said buried bit line regions.
Claim 12
Independent Claim
280 words
A method of fabricating a read only memory, (ROM), cell on a semiconductor substrate, having a first conductivity, comprising the steps of: forming a field oxide pattern on regions of said substrate, while leaving silicon unoxidized on remaining regions of said substrate photolithography to expose portions of said unoxidized silicon; ion implanting second conductivity imparting dopants into said exposed portions of said unoxidized silicon, to form buried bit line regions; growing a first oxide layer on said buried bit line regions; growing a second oxide layer on non-implanted silicon regions, said first oxide layer having a thickness greater than a thickness of said second oxide layer; photolithography to expose a specific area of said first oxide layer, grown on said buried bit line regions to program said ROM cell; removal of said first oxide layer, from said specific area of said buried bit line regions; depositing a polysilicon layer on said field oxide, on said second oxide layer on said non-ion implanted silicon, on said first oxide layer grown on said buried bit line regions, and on said buried bit line regions, in specific area where said first oxide layer has been removed; ion implanting a first conductivity imparting dopant into said polysilicon layer; annealing to drive, said first conductivity imparting dopant, into said specific area of said buried bit line regions, where said first oxide layer has been removed, to form a diode; and patterning said polysilicon layer to form a word line on said field oxide, on said second oxide layer on said non-ion implanted silicon, on said first oxide layer on said buried bit line regions, and on said diode, formed in said buried bit line regions.
Claim 13
Dependent Claim
20 words
The method of claim 10, wherein said field oxide is grown to a thickness between about 4000 to 6000 Angstroms.
Claim 14
Dependent Claim
62 words
The method of claim 10, wherein said second conductivity dopants, used to create said buried bit line regions, are arsenic, ion implanted at an energy between about 50 to 100 Kev., at a dose between about 1E14 to 1E16 atoms/cm2, and phosphorous, ion implanted at an energy between about 30 to 60 Kev., at a dose between about 1E14 to 1E16 atoms/cm2.
Claim 15
Dependent Claim
37 words
The method of claim 10, wherein said first oxide layer grown on said buried bit line regions, is grown at a temperature between about 850° to 950° C., to a thickness between about 800 to 2000 Angstroms.
Claim 16
Dependent Claim
36 words
The method of claim 10, wherein said second oxide layer grown on said non-ion implanted silicon, is grown at a temperature between about 850° to 950° C., to a thickness between about 400 to 1000 Angstroms.
Claim 17
Dependent Claim
30 words
The method of claim 10, wherein removal of said first oxide layer, from said specific area of said buried bit line regions, is accomplished using a buffered hydrofluoric acid solution.
Claim 18
Dependent Claim
20 words
The method of claim 10, wherein said polysilicon layer is deposited to a thickness between about 1200 to 1800 Angstroms.
Claim 19
Dependent Claim
33 words
The method of claim 10, wherein said first conductivity imparting dopant is boron, ion implanted at an energy between about 30 to 60 Kev., at a dose between about 1E14 to 1E16 atoms/cm2.
Claim 20
Dependent Claim
39 words
The method of claim 10, wherein said anneal, used to create said diode in said buried bit line regions is performed at a temperature between about 850° and 950° C., for a time between about 30 to 60 min.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |